JPS5585041A - Semiconductor device and its preparation - Google Patents

Semiconductor device and its preparation

Info

Publication number
JPS5585041A
JPS5585041A JP15744478A JP15744478A JPS5585041A JP S5585041 A JPS5585041 A JP S5585041A JP 15744478 A JP15744478 A JP 15744478A JP 15744478 A JP15744478 A JP 15744478A JP S5585041 A JPS5585041 A JP S5585041A
Authority
JP
Japan
Prior art keywords
electrode
high concentration
connecting holes
injected
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15744478A
Other languages
Japanese (ja)
Other versions
JPS6138858B2 (en
Inventor
Yasunobu Osa
Tatsumi Shirasu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15744478A priority Critical patent/JPS5585041A/en
Publication of JPS5585041A publication Critical patent/JPS5585041A/en
Publication of JPS6138858B2 publication Critical patent/JPS6138858B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: To prevent the lowering of reliability due to the positional slippage of a pattern and overetching, by a method wherein connecting holes are opened to an insulating film, phospher ions with high concentration are injected, activated, thermally treated and electrode wiring is formed.
CONSTITUTION: A thick oxide film 3, a gate oxide film, a polysilicon gate electrode, a source 12a and a drain 12b are made up on a p-type Si wafer 1. A PSG film 4 is built up, and electrode connecting holes 6aW6c are opened by selectively etching the film 4. Phosphor ions are injected in high concentration, and impurities injected in ionic shapes are activated and thermally treated. Al is evaporated, and an electrode is formed by means of a photo-etching method. Even when the locations of the electrode connecting holes are shifted from a n+-layer, the portions also become to n-type high concentration regions beforehand by the injection of the phosphor ions with high concentration, electrode wiring does not connect with a substrate, and the production of defective characteristics can be prevented.
COPYRIGHT: (C)1980,JPO&Japio
JP15744478A 1978-12-22 1978-12-22 Semiconductor device and its preparation Granted JPS5585041A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15744478A JPS5585041A (en) 1978-12-22 1978-12-22 Semiconductor device and its preparation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15744478A JPS5585041A (en) 1978-12-22 1978-12-22 Semiconductor device and its preparation

Publications (2)

Publication Number Publication Date
JPS5585041A true JPS5585041A (en) 1980-06-26
JPS6138858B2 JPS6138858B2 (en) 1986-09-01

Family

ID=15649781

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15744478A Granted JPS5585041A (en) 1978-12-22 1978-12-22 Semiconductor device and its preparation

Country Status (1)

Country Link
JP (1) JPS5585041A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58110037A (en) * 1981-12-24 1983-06-30 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
US5051377A (en) * 1988-09-01 1991-09-24 International Business Machines Corporation Method for forming a thin dielectric layer on a substrate
US5139869A (en) * 1988-09-01 1992-08-18 Wolfgang Euen Thin dielectric layer on a substrate
US5268311A (en) * 1988-09-01 1993-12-07 International Business Machines Corporation Method for forming a thin dielectric layer on a substrate
JPH07263556A (en) * 1995-03-24 1995-10-13 Hitachi Ltd Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58110037A (en) * 1981-12-24 1983-06-30 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
US5051377A (en) * 1988-09-01 1991-09-24 International Business Machines Corporation Method for forming a thin dielectric layer on a substrate
US5139869A (en) * 1988-09-01 1992-08-18 Wolfgang Euen Thin dielectric layer on a substrate
US5268311A (en) * 1988-09-01 1993-12-07 International Business Machines Corporation Method for forming a thin dielectric layer on a substrate
JPH07263556A (en) * 1995-03-24 1995-10-13 Hitachi Ltd Semiconductor device

Also Published As

Publication number Publication date
JPS6138858B2 (en) 1986-09-01

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