JPS5745947A - Mos type semiconductor integrated circuit - Google Patents

Mos type semiconductor integrated circuit

Info

Publication number
JPS5745947A
JPS5745947A JP55121894A JP12189480A JPS5745947A JP S5745947 A JPS5745947 A JP S5745947A JP 55121894 A JP55121894 A JP 55121894A JP 12189480 A JP12189480 A JP 12189480A JP S5745947 A JPS5745947 A JP S5745947A
Authority
JP
Japan
Prior art keywords
layer
insulating layer
film
substrate
field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55121894A
Other languages
Japanese (ja)
Inventor
Shigeru Morita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55121894A priority Critical patent/JPS5745947A/en
Publication of JPS5745947A publication Critical patent/JPS5745947A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/191—Preparing SOI wafers using full isolation by porous oxide silicon [FIPOS]

Landscapes

  • Element Separation (AREA)

Abstract

PURPOSE:To obtain an MOS device which has no erroneous operation and the stepwise disconnection of a wire by forming a field insulating layer consecutively integrally with a buried type insulation isolating layer. CONSTITUTION:A resist mask 9 is covered on an SiO2 film 2 on a P type Si substrate 1. When a CF4 plasma is emitted to the film, the film is then etched with NH4F to form a hole 10 having a flaw. The mask 9 is removed, an O2 ion injecting layer 11 is formed, the layer is treated at higher thabn 1,100 deg.C, and a wavy thin insulaing layer 2 made of a field insulating layer 2b consecutive to a buried insulating layer 2a is formed. Thereafter, a memory cell MC, a wiring diffused layer C, and MOS transistor Q are formed on the region surrounded by an insulating layer 1a. Since the minority carrier due to the operation of the Q does not flow to the MC, the erroneous operation can be prevented with no leakage due to the inversion of the field and the layer 2b can be reduced in thickness with this configuration, the surface of the substrate can be smoothened, and no stepwise disconnection of the wire occurs.
JP55121894A 1980-09-03 1980-09-03 Mos type semiconductor integrated circuit Pending JPS5745947A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55121894A JPS5745947A (en) 1980-09-03 1980-09-03 Mos type semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55121894A JPS5745947A (en) 1980-09-03 1980-09-03 Mos type semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5745947A true JPS5745947A (en) 1982-03-16

Family

ID=14822530

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55121894A Pending JPS5745947A (en) 1980-09-03 1980-09-03 Mos type semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5745947A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6242556A (en) * 1985-08-20 1987-02-24 Matsushita Electronics Corp Manufacture of semiconductor device
US4713678A (en) * 1984-12-07 1987-12-15 Texas Instruments Incorporated dRAM cell and method
JPH0291973A (en) * 1988-09-29 1990-03-30 Toshiba Corp Manufacture of semiconductor device
US5034335A (en) * 1987-05-26 1991-07-23 U.S. Philips Corp. Method of manufacturing a silicon on insulator (SOI) semiconductor device
JPH07109872B1 (en) * 1987-10-08 1995-11-22 Matsushita Electric Ind Co Ltd
JPH1012850A (en) * 1995-12-30 1998-01-16 Hyundai Electron Ind Co Ltd SOI substrate and manufacturing method thereof
US6197656B1 (en) 1998-03-24 2001-03-06 International Business Machines Corporation Method of forming planar isolation and substrate contacts in SIMOX-SOI.

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5116268A (en) * 1974-07-31 1976-02-09 Sumitomo Metal Ind DAISUSHUGOTAIBUNKAIKUMITATESOCHI
JPS5153488A (en) * 1974-11-06 1976-05-11 Hitachi Ltd HANDOTAISHUSEKIKAIROYOKIBANNO SEIHO

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5116268A (en) * 1974-07-31 1976-02-09 Sumitomo Metal Ind DAISUSHUGOTAIBUNKAIKUMITATESOCHI
JPS5153488A (en) * 1974-11-06 1976-05-11 Hitachi Ltd HANDOTAISHUSEKIKAIROYOKIBANNO SEIHO

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4713678A (en) * 1984-12-07 1987-12-15 Texas Instruments Incorporated dRAM cell and method
JPS6242556A (en) * 1985-08-20 1987-02-24 Matsushita Electronics Corp Manufacture of semiconductor device
US5034335A (en) * 1987-05-26 1991-07-23 U.S. Philips Corp. Method of manufacturing a silicon on insulator (SOI) semiconductor device
JPH07109872B1 (en) * 1987-10-08 1995-11-22 Matsushita Electric Ind Co Ltd
JPH0291973A (en) * 1988-09-29 1990-03-30 Toshiba Corp Manufacture of semiconductor device
JPH1012850A (en) * 1995-12-30 1998-01-16 Hyundai Electron Ind Co Ltd SOI substrate and manufacturing method thereof
US6197656B1 (en) 1998-03-24 2001-03-06 International Business Machines Corporation Method of forming planar isolation and substrate contacts in SIMOX-SOI.

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