JPS5585158A - Constitution for buffer memory of data exchanger - Google Patents

Constitution for buffer memory of data exchanger

Info

Publication number
JPS5585158A
JPS5585158A JP15952978A JP15952978A JPS5585158A JP S5585158 A JPS5585158 A JP S5585158A JP 15952978 A JP15952978 A JP 15952978A JP 15952978 A JP15952978 A JP 15952978A JP S5585158 A JPS5585158 A JP S5585158A
Authority
JP
Japan
Prior art keywords
mmu
memory
data
constitution
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15952978A
Other languages
Japanese (ja)
Inventor
Tsugio Sugawara
Kenichi Hanabe
Toru Nakagawa
Isamu Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
NEC Corp
NTT Inc
Original Assignee
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP15952978A priority Critical patent/JPS5585158A/en
Publication of JPS5585158A publication Critical patent/JPS5585158A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/50—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication
    • H04L12/52—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication using time division techniques
    • H04L12/525—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication using time division techniques involving a stored program control

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer And Data Communications (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE:To avoid the overflow and to increase the efficiency, by constituting the buffer memory proportional to the call of the line with the memory of common management. CONSTITUTION:The memory managing unit (MMU) represents the transmission or exclusive reception, and a plurality of lines are contained in each MMU, and the buffers, minimum two, are assigned to each line as the buffers 5, 6, 7. The multiplexer MPX controls the data flow between each MMU and main memory MM10 and selects MMU coupled with the main memory MM9. For example, MMU1 and 2 receive the data from the line correspondence section and every time one buffer is full, data is transferred to MM9 via MPX8 and another buffer operates as the reception data area to perform continuous reception.
JP15952978A 1978-12-21 1978-12-21 Constitution for buffer memory of data exchanger Pending JPS5585158A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15952978A JPS5585158A (en) 1978-12-21 1978-12-21 Constitution for buffer memory of data exchanger

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15952978A JPS5585158A (en) 1978-12-21 1978-12-21 Constitution for buffer memory of data exchanger

Publications (1)

Publication Number Publication Date
JPS5585158A true JPS5585158A (en) 1980-06-26

Family

ID=15695749

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15952978A Pending JPS5585158A (en) 1978-12-21 1978-12-21 Constitution for buffer memory of data exchanger

Country Status (1)

Country Link
JP (1) JPS5585158A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5837740A (en) * 1981-08-31 1983-03-05 Nippon Telegr & Teleph Corp <Ntt> Buffer memory controlling system
JPS58161038A (en) * 1982-03-19 1983-09-24 Fujitsu Ltd Buffer managing system
JPH0685842A (en) * 1991-11-29 1994-03-25 American Teleph & Telegr Co <Att> Communication device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4861004A (en) * 1971-12-01 1973-08-27
JPS5026018A (en) * 1973-07-06 1975-03-18
JPS5045510A (en) * 1973-08-25 1975-04-23
JPS5299422A (en) * 1976-02-17 1977-08-20 Isono Tetsukou Kk Method of assembling tank side walls
JPS52112245A (en) * 1976-03-17 1977-09-20 Hitachi Ltd Data terminal unit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4861004A (en) * 1971-12-01 1973-08-27
JPS5026018A (en) * 1973-07-06 1975-03-18
JPS5045510A (en) * 1973-08-25 1975-04-23
JPS5299422A (en) * 1976-02-17 1977-08-20 Isono Tetsukou Kk Method of assembling tank side walls
JPS52112245A (en) * 1976-03-17 1977-09-20 Hitachi Ltd Data terminal unit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5837740A (en) * 1981-08-31 1983-03-05 Nippon Telegr & Teleph Corp <Ntt> Buffer memory controlling system
JPS58161038A (en) * 1982-03-19 1983-09-24 Fujitsu Ltd Buffer managing system
JPH0685842A (en) * 1991-11-29 1994-03-25 American Teleph & Telegr Co <Att> Communication device

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