JPS5585933A - Interruption signal generating circuit - Google Patents

Interruption signal generating circuit

Info

Publication number
JPS5585933A
JPS5585933A JP16385578A JP16385578A JPS5585933A JP S5585933 A JPS5585933 A JP S5585933A JP 16385578 A JP16385578 A JP 16385578A JP 16385578 A JP16385578 A JP 16385578A JP S5585933 A JPS5585933 A JP S5585933A
Authority
JP
Japan
Prior art keywords
input
output
changes
interruption signal
produce
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16385578A
Other languages
Japanese (ja)
Inventor
Masae Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP16385578A priority Critical patent/JPS5585933A/en
Publication of JPS5585933A publication Critical patent/JPS5585933A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To produce interruption signal with less number of components, by constitution of the exclusive logical sum circuit and several other logic circuits.
CONSTITUTION: A number of ON-OFF signal inputs such as relay contacts are present by 1WN. Assuming that the input 2 changes from OFF to ON and the input 4 from ON to OFF, and when N is an even number, since the input 4 is already ON, the output A of the exclusive logical sum circuit F is logic level 1. When the input 2 changes from OFF to ON, since the output A is 0, FFH is operative and the output B passes through the logic circuit J into the output D to produce the interruption signal. When the computer is finished for the data read-in, the reset pulse signal E is outputted to reset FFH under operation. Similarly, when the input 4 changes from ON to OFF, since the output A of the circuit F changes from 0 to 1, FFI is operative to produce the interruption signal.
COPYRIGHT: (C)1980,JPO&Japio
JP16385578A 1978-12-22 1978-12-22 Interruption signal generating circuit Pending JPS5585933A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16385578A JPS5585933A (en) 1978-12-22 1978-12-22 Interruption signal generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16385578A JPS5585933A (en) 1978-12-22 1978-12-22 Interruption signal generating circuit

Publications (1)

Publication Number Publication Date
JPS5585933A true JPS5585933A (en) 1980-06-28

Family

ID=15782025

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16385578A Pending JPS5585933A (en) 1978-12-22 1978-12-22 Interruption signal generating circuit

Country Status (1)

Country Link
JP (1) JPS5585933A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59160223A (en) * 1983-03-03 1984-09-10 Mitsubishi Electric Corp Signal input device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59160223A (en) * 1983-03-03 1984-09-10 Mitsubishi Electric Corp Signal input device

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