JPS5586271A - Synchronizing signal generator - Google Patents

Synchronizing signal generator

Info

Publication number
JPS5586271A
JPS5586271A JP16380978A JP16380978A JPS5586271A JP S5586271 A JPS5586271 A JP S5586271A JP 16380978 A JP16380978 A JP 16380978A JP 16380978 A JP16380978 A JP 16380978A JP S5586271 A JPS5586271 A JP S5586271A
Authority
JP
Japan
Prior art keywords
signal
counter
synchronizing frequency
constant
forms
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16380978A
Other languages
Japanese (ja)
Other versions
JPS6129596B2 (en
Inventor
Takashi Nakamura
Akira Taki
Mitsunori Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP16380978A priority Critical patent/JPS5586271A/en
Publication of JPS5586271A publication Critical patent/JPS5586271A/en
Publication of JPS6129596B2 publication Critical patent/JPS6129596B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Processing Of Color Television Signals (AREA)

Abstract

PURPOSE: To bear a constant phase relation among a horizontal synchronizing frequency signal, chrominance subcarrier signal and color framing signal, and that between them and a vertical synchronizing frequency signal, by controlling a counter by the color framing signal.
CONSTITUTION: The output of reference signal oscillator 1 is divided by divider 2 to generate a synchronizing frequency twice a horizontal frequency and it is further supplied to 1/2 counter 3, which forms vertical synchronizing frequency Sv. Counter 5 is a 1/4 counter and forms chrominance subcarrier signal Ssc. Formation circuit 10 forms color framing signal PD corresponding to the number of fields where the phase of signal Ssc makes a round. Here, control is exercised by normalizing signal PD into reference signal S0 to absorb variation. For the purpose, signal PD is normalized into signal S0 by normalizing circuits 20A and 20B. Then, the control timing of counter 5 is made invariably constant by signal S0, so that phase relations will be constant.
COPYRIGHT: (C)1980,JPO&Japio
JP16380978A 1978-12-22 1978-12-22 Synchronizing signal generator Granted JPS5586271A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16380978A JPS5586271A (en) 1978-12-22 1978-12-22 Synchronizing signal generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16380978A JPS5586271A (en) 1978-12-22 1978-12-22 Synchronizing signal generator

Publications (2)

Publication Number Publication Date
JPS5586271A true JPS5586271A (en) 1980-06-28
JPS6129596B2 JPS6129596B2 (en) 1986-07-08

Family

ID=15781110

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16380978A Granted JPS5586271A (en) 1978-12-22 1978-12-22 Synchronizing signal generator

Country Status (1)

Country Link
JP (1) JPS5586271A (en)

Also Published As

Publication number Publication date
JPS6129596B2 (en) 1986-07-08

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