JPS5587085A - Timer - Google Patents

Timer

Info

Publication number
JPS5587085A
JPS5587085A JP16226278A JP16226278A JPS5587085A JP S5587085 A JPS5587085 A JP S5587085A JP 16226278 A JP16226278 A JP 16226278A JP 16226278 A JP16226278 A JP 16226278A JP S5587085 A JPS5587085 A JP S5587085A
Authority
JP
Japan
Prior art keywords
timer
time
display
data
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16226278A
Other languages
Japanese (ja)
Inventor
Takuji Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu General Ltd
Gen Co Ltd
Original Assignee
Fujitsu General Ltd
Gen Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu General Ltd, Gen Co Ltd filed Critical Fujitsu General Ltd
Priority to JP16226278A priority Critical patent/JPS5587085A/en
Publication of JPS5587085A publication Critical patent/JPS5587085A/en
Pending legal-status Critical Current

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  • Electric Clocks (AREA)

Abstract

PURPOSE: To perform the display whether the ON-OFF time set two or more is normal or abnormal, by the comparison and judgement of the ON-OFF timer data information of a plurality stored and set through substraction.
CONSTITUTION: The timer ON-OFF time A, B once are set and stored in the data memories 4, 5 via the set data input unit 1 and multiplexer 3. Further, the timer ON time C at second times is set and stored in the data memory 6 via the sequence input unit 2 and multiplexer 3, then the subtraction circuits 8, 10 perform the subtraction of (B-A), (C-A) respectively. If (C-A)<(B-A) is not satisfied, the comparison circuit 15 produces failure judgement signal. This signal is inputted to the input data failure normal display circuit 24 via the gate circuit 20. The output of the circuit 24 displays the abnormal set due to contradiction of the set time on the display unit 8. The contradictions of the timer ON-OFF time set two or more are similarly processed to display the set for normal or abnormal display.
COPYRIGHT: (C)1980,JPO&Japio
JP16226278A 1978-12-25 1978-12-25 Timer Pending JPS5587085A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16226278A JPS5587085A (en) 1978-12-25 1978-12-25 Timer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16226278A JPS5587085A (en) 1978-12-25 1978-12-25 Timer

Publications (1)

Publication Number Publication Date
JPS5587085A true JPS5587085A (en) 1980-07-01

Family

ID=15751092

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16226278A Pending JPS5587085A (en) 1978-12-25 1978-12-25 Timer

Country Status (1)

Country Link
JP (1) JPS5587085A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5066111A (en) * 1973-10-12 1975-06-04
JPS53130077A (en) * 1977-04-19 1978-11-13 Omron Tateisi Electronics Co Overlap setting preventing device of timers

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5066111A (en) * 1973-10-12 1975-06-04
JPS53130077A (en) * 1977-04-19 1978-11-13 Omron Tateisi Electronics Co Overlap setting preventing device of timers

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