JPS5590893A - Timer - Google Patents

Timer

Info

Publication number
JPS5590893A
JPS5590893A JP16220778A JP16220778A JPS5590893A JP S5590893 A JPS5590893 A JP S5590893A JP 16220778 A JP16220778 A JP 16220778A JP 16220778 A JP16220778 A JP 16220778A JP S5590893 A JPS5590893 A JP S5590893A
Authority
JP
Japan
Prior art keywords
signal
clock
turned
adj
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16220778A
Other languages
Japanese (ja)
Other versions
JPS6129476B2 (en
Inventor
Masao Ito
Shinichi Nakane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP16220778A priority Critical patent/JPS5590893A/en
Publication of JPS5590893A publication Critical patent/JPS5590893A/en
Publication of JPS6129476B2 publication Critical patent/JPS6129476B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Electric Clocks (AREA)

Abstract

PURPOSE: To prevent the time shown on a clock from being changed by accident when a timer provided therein is set, by furnishing the timer with an ability to prevent, after a power source has been turned on and after the time has then been set, the time shown on the clock from being corrected unless the power source is turned off.
CONSTITUTION: After a power source has been turned on, an output RST from an inverter 84 is changed from one to zero. R-S flip-flops (FF) 85, 86 are reset while the RST signal is one. When a register key is depressed after a clock correction mode has been obtained, a clock correction signal ADJ and a register signal NUM are input into an AND circuit 80, and FF85 is set with an output signal from the AND circuit 80. As a result, a latch signal LAT is output from FF85, and ADJ.IN signal is turned to be one, so that the time shown on the clock is ready to be corrected. When the clock correction mode is then shifted to a clock mode, a signal LAT and a clock signal CLK are input into an AND circuit 81 so that FF86 is set to output a signal SET. Even when ADJ signal is thereafter generated, the time shown on the clock cannot be correced since ADJ.IN signal has been turned to zero.
COPYRIGHT: (C)1980,JPO&Japio
JP16220778A 1978-12-29 1978-12-29 Timer Granted JPS5590893A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16220778A JPS5590893A (en) 1978-12-29 1978-12-29 Timer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16220778A JPS5590893A (en) 1978-12-29 1978-12-29 Timer

Publications (2)

Publication Number Publication Date
JPS5590893A true JPS5590893A (en) 1980-07-09
JPS6129476B2 JPS6129476B2 (en) 1986-07-07

Family

ID=15749999

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16220778A Granted JPS5590893A (en) 1978-12-29 1978-12-29 Timer

Country Status (1)

Country Link
JP (1) JPS5590893A (en)

Also Published As

Publication number Publication date
JPS6129476B2 (en) 1986-07-07

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