JPS5595444A - Externally-synchronous scrambler/descrambler system - Google Patents
Externally-synchronous scrambler/descrambler systemInfo
- Publication number
- JPS5595444A JPS5595444A JP356979A JP356979A JPS5595444A JP S5595444 A JPS5595444 A JP S5595444A JP 356979 A JP356979 A JP 356979A JP 356979 A JP356979 A JP 356979A JP S5595444 A JPS5595444 A JP S5595444A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- level
- dscr
- frame
- initial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To attain the acquisition of synchronism in a short time while preventing an influence of a transmission error of a reception side, by using an external synchronization system for multi-level transmission. CONSTITUTION:Input information signal INS is made random by scrambler SCR and a multi-level signal from multi-leveling COD is transmitted with a frame signal added COD; and a reception side converts DEC the multi-level signal into a binary signal and then regenerates the same signal as signal INS by descrambler DSCR. In this case, SCR and DSCR are equipped with random pulse generation parts RG1, RG2 and RG3 respectively, and RG2 is initialized by the output signal of RG1 and actuated by a pulse of a frame period. Then, the initial-state setting information of RG 2 is inserted by a frame signal by a specific level of the multi-level signal and sent out, and DSCR is actuated according to initial-state information expressed by the level of the frame signal received.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP356979A JPS5595444A (en) | 1979-01-16 | 1979-01-16 | Externally-synchronous scrambler/descrambler system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP356979A JPS5595444A (en) | 1979-01-16 | 1979-01-16 | Externally-synchronous scrambler/descrambler system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5595444A true JPS5595444A (en) | 1980-07-19 |
Family
ID=11561063
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP356979A Pending JPS5595444A (en) | 1979-01-16 | 1979-01-16 | Externally-synchronous scrambler/descrambler system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5595444A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60210044A (en) * | 1984-04-03 | 1985-10-22 | Nec Corp | Transmitting and receiving device of error correction code |
| JPH0411424A (en) * | 1990-04-27 | 1992-01-16 | Nec Corp | Reset type scramble code transmission system |
-
1979
- 1979-01-16 JP JP356979A patent/JPS5595444A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60210044A (en) * | 1984-04-03 | 1985-10-22 | Nec Corp | Transmitting and receiving device of error correction code |
| JPH0411424A (en) * | 1990-04-27 | 1992-01-16 | Nec Corp | Reset type scramble code transmission system |
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