JPS5597733A - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPS5597733A
JPS5597733A JP513079A JP513079A JPS5597733A JP S5597733 A JPS5597733 A JP S5597733A JP 513079 A JP513079 A JP 513079A JP 513079 A JP513079 A JP 513079A JP S5597733 A JPS5597733 A JP S5597733A
Authority
JP
Japan
Prior art keywords
power supply
responsiveness
logical level
circuit
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP513079A
Other languages
Japanese (ja)
Inventor
Yoji Hirano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP513079A priority Critical patent/JPS5597733A/en
Publication of JPS5597733A publication Critical patent/JPS5597733A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To improve responsiveness by providing a capacitor between connection points in a circuit which extracts outputs from connection parts of cascaded transistors. CONSTITUTION:In a circuit which holds a high-rank power supply at a stable logical level and a low-rank power supply at a stable logical level, difference V1 in input logical level between input terminals 13 and 14 fixes forward voltages of transistors Q13 and Q14 to VF and voltage VF-V1 or VF+V1 appears at output terminal 15. This shows that the output voltage has no relation to the voltage of power supply 11. Since the responsiveness of this circuit depends chiefly upon resistances R11 and R12, capacitors C11 and C12 connected in parallel serve as speed- up capacitors, so that the responsiveness will be improved.
JP513079A 1979-01-19 1979-01-19 Logic circuit Pending JPS5597733A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP513079A JPS5597733A (en) 1979-01-19 1979-01-19 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP513079A JPS5597733A (en) 1979-01-19 1979-01-19 Logic circuit

Publications (1)

Publication Number Publication Date
JPS5597733A true JPS5597733A (en) 1980-07-25

Family

ID=11602724

Family Applications (1)

Application Number Title Priority Date Filing Date
JP513079A Pending JPS5597733A (en) 1979-01-19 1979-01-19 Logic circuit

Country Status (1)

Country Link
JP (1) JPS5597733A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0263318A (en) * 1988-05-27 1990-03-02 Texas Instr Inc <Ti> Level convertion circuit from mos to ecl

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4952959A (en) * 1972-07-03 1974-05-23
JPS527974A (en) * 1975-07-08 1977-01-21 Asahi Chem Ind Co Ltd Process for preparing n4- acylcytarabines

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4952959A (en) * 1972-07-03 1974-05-23
JPS527974A (en) * 1975-07-08 1977-01-21 Asahi Chem Ind Co Ltd Process for preparing n4- acylcytarabines

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0263318A (en) * 1988-05-27 1990-03-02 Texas Instr Inc <Ti> Level convertion circuit from mos to ecl

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