JPS5599761A - Manufacutre of integrated circuit device - Google Patents

Manufacutre of integrated circuit device

Info

Publication number
JPS5599761A
JPS5599761A JP712479A JP712479A JPS5599761A JP S5599761 A JPS5599761 A JP S5599761A JP 712479 A JP712479 A JP 712479A JP 712479 A JP712479 A JP 712479A JP S5599761 A JPS5599761 A JP S5599761A
Authority
JP
Japan
Prior art keywords
type
forming
region
regions
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP712479A
Other languages
Japanese (ja)
Inventor
Yasunobu Tanizaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP712479A priority Critical patent/JPS5599761A/en
Publication of JPS5599761A publication Critical patent/JPS5599761A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/611—Combinations of BJTs and one or more of diodes, resistors or capacitors
    • H10D84/613—Combinations of vertical BJTs and one or more of diodes, resistors or capacitors
    • H10D84/617—Combinations of vertical BJTs and only diodes

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

PURPOSE:To improve linearity by forming a schottky barrier diode by the process same as used in, and simultaneously with, forming an ohmic contact to a transistor. CONSTITUTION:DI is the log diode and TR is the transistor. After N-type silicon layer is epitaxially grown on the surface of P-type Si substrate 10 via N<+>-buried-in layer 12, P-type region 16 is formed by using Si oxide film 14 as a mask and diffusing an acceptor impurity, and the N-type Si region is separated into regions 18A and 18B. P-type base region 20 is formed in region 18B, and then N<+>-type regions 22, 26 and 24 are formed in regions 18A, 18B and 20. Next, Schottky barrier forming Al layer 28 contact forming Al layers 30, 32, 34 and 36 are formed.
JP712479A 1979-01-26 1979-01-26 Manufacutre of integrated circuit device Pending JPS5599761A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP712479A JPS5599761A (en) 1979-01-26 1979-01-26 Manufacutre of integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP712479A JPS5599761A (en) 1979-01-26 1979-01-26 Manufacutre of integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5599761A true JPS5599761A (en) 1980-07-30

Family

ID=11657319

Family Applications (1)

Application Number Title Priority Date Filing Date
JP712479A Pending JPS5599761A (en) 1979-01-26 1979-01-26 Manufacutre of integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5599761A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4492972A (en) * 1981-08-17 1985-01-08 Honeywell Inc. JFET Monolithic integrated circuit with input bias current temperature compensation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4492972A (en) * 1981-08-17 1985-01-08 Honeywell Inc. JFET Monolithic integrated circuit with input bias current temperature compensation

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