JPS56100435A - Face-down bonder - Google Patents

Face-down bonder

Info

Publication number
JPS56100435A
JPS56100435A JP206680A JP206680A JPS56100435A JP S56100435 A JPS56100435 A JP S56100435A JP 206680 A JP206680 A JP 206680A JP 206680 A JP206680 A JP 206680A JP S56100435 A JPS56100435 A JP S56100435A
Authority
JP
Japan
Prior art keywords
pattern
chip
substrate
block
photopath
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP206680A
Other languages
Japanese (ja)
Other versions
JPS6239537B2 (en
Inventor
Osamu Tachibana
Tetsuo Noguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP206680A priority Critical patent/JPS56100435A/en
Publication of JPS56100435A publication Critical patent/JPS56100435A/en
Publication of JPS6239537B2 publication Critical patent/JPS6239537B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07178—Means for aligning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To perform position matching by a method wherein the surface of a substrate on a block and the lower surface of a chip in a supporting tool are projected by an optical system, two photopaths are intercepted alternately, a pattern obtained from the optical system is binarized to determine a position, the amount of slippage from a reference pattern is calculated and the block or supporting tool is controlled and moved. CONSTITUTION:The substrate 3 and the chip 1 are fitted to the block 5 and the supporting tool 13 respectively, a shutter 21 is advance to intercept the photopath of a chip pattern, while a substrate pattern is projected on the screen of TV16, binatized 23, compared 24 with the reference pattern to calculate 25 the amount of slippage, and the block 5 is controlled and driven 26 to turn the slippage into zero. Next, a shutter 22 is advanced to intercept the photopath 18 of the substrate pattern, the photopath 17 is opened to project the chip pattern on the screen of TV16, whereby it is made to accord with the reference pattern. As the result, the chip pattern is correctly positioned on the substrate pattern. Then, the shutter 22 is moved back, a supporting body 14 is made to approach the block 5 and the bump electrode 2 of the chip 1 is laid on the wiring layer 4 of the substrate 3 to be heated for connection. By this constitution, the position matching can be performed automatically and thereby the efficiency of operation is improved.
JP206680A 1980-01-14 1980-01-14 Face-down bonder Granted JPS56100435A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP206680A JPS56100435A (en) 1980-01-14 1980-01-14 Face-down bonder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP206680A JPS56100435A (en) 1980-01-14 1980-01-14 Face-down bonder

Publications (2)

Publication Number Publication Date
JPS56100435A true JPS56100435A (en) 1981-08-12
JPS6239537B2 JPS6239537B2 (en) 1987-08-24

Family

ID=11518962

Family Applications (1)

Application Number Title Priority Date Filing Date
JP206680A Granted JPS56100435A (en) 1980-01-14 1980-01-14 Face-down bonder

Country Status (1)

Country Link
JP (1) JPS56100435A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01119031A (en) * 1987-10-31 1989-05-11 Nec Corp Pellet bonding device
WO2024014077A1 (en) * 2022-07-11 2024-01-18 パナソニックIpマネジメント株式会社 Positioning device, mounting device, positioning method and mounting method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01119031A (en) * 1987-10-31 1989-05-11 Nec Corp Pellet bonding device
WO2024014077A1 (en) * 2022-07-11 2024-01-18 パナソニックIpマネジメント株式会社 Positioning device, mounting device, positioning method and mounting method

Also Published As

Publication number Publication date
JPS6239537B2 (en) 1987-08-24

Similar Documents

Publication Publication Date Title
BG50833A3 (en) Process for coating glass
DE3686457D1 (en) METHOD FOR PRODUCING A SEMICONDUCTOR APPARATUS WITH TWO SEMICONDUCTOR ARRANGEMENTS.
BG50832A3 (en) Method and device for coating glass
EP0148448A3 (en) Etching method
ATE163800T1 (en) METHOD AND DEVICE FOR STACKING SUBSTRATES TO BE CONNECTED TO EACH OTHER BY BONDING
DE69125268D1 (en) METHOD AND DEVICE FOR PRODUCING TRANSITIONS BY DIFFUSION IN SUBSTRATES OF SOLAR CELLS
JPS57173952A (en) Positioning method of semiconductor chip
JPS57147245A (en) Positioning method and device for chip bonding
JPS5286546A (en) Microwave heating device
JPS5763844A (en) Dividing method for semiconductor wafer
JPS5640252A (en) Transfer positioning device for chip bonder
JPS53133366A (en) Impurity diffusion method
JPS5427364A (en) Metal wire bonding method for semiconductor device
JPS5271981A (en) Aligning device for bonders
JPS5754024A (en) Second-cut processing method for male part of workpiece
JPS6410636A (en) Manufacture of hybrid integrated circuit
JPS5432978A (en) Correcting method for pattern
JPS5413264A (en) Bonding method of semiconductor chip
JPS52127072A (en) Wire bonding apparatus
JPS5419624A (en) Adhering method of adhesive tape
JPS5379382A (en) Forming method of passivation film
JPS5424380A (en) Work clamping device for machining tools
JPS5216971A (en) Base plate heat treatment method and wafer for semiconductor
JPS5723234A (en) Pattern detecting method of full automatic wire bonding
JPS57206040A (en) Wire bonding method