JPS56105653A - Gold bump forming method of semiconductor device - Google Patents

Gold bump forming method of semiconductor device

Info

Publication number
JPS56105653A
JPS56105653A JP861380A JP861380A JPS56105653A JP S56105653 A JPS56105653 A JP S56105653A JP 861380 A JP861380 A JP 861380A JP 861380 A JP861380 A JP 861380A JP S56105653 A JPS56105653 A JP S56105653A
Authority
JP
Japan
Prior art keywords
layer
bump
resist mask
metal
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP861380A
Other languages
Japanese (ja)
Inventor
Kenichi Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP861380A priority Critical patent/JPS56105653A/en
Publication of JPS56105653A publication Critical patent/JPS56105653A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To contrive an increase of junction strength by removing a conducting metal layer and subsequently forming the Au bump by applying an electroplating, after a three layers structure of a groundwork metal, intermediate metal and conducting metal is accumulated on a substrate and a resist mask is mounted. CONSTITUTION:An SiO2 film 3 is formed with an opening to allow the Cr groundwork layer 4, Au intermediate layer 5a and Cu conductive layer 8 to be layer-built on an Al electrode 2 on the Si substrate 1. The resist mask 6 is applied to eause the Cu layer 8 to be etched, the Au 5a to be exposed and the Au bump to be formed by the electroplating. Then, by removing the resist mask 6 and etching the Cu 8, Au 5a, Cr 4 with the Au bump 7 as a mask, the Au bump 7 extremely high in junction strength is finished. With such a method, the adhesive strength is not decreased at 11 by the remained resist thin film as conventional.
JP861380A 1980-01-28 1980-01-28 Gold bump forming method of semiconductor device Pending JPS56105653A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP861380A JPS56105653A (en) 1980-01-28 1980-01-28 Gold bump forming method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP861380A JPS56105653A (en) 1980-01-28 1980-01-28 Gold bump forming method of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56105653A true JPS56105653A (en) 1981-08-22

Family

ID=11697795

Family Applications (1)

Application Number Title Priority Date Filing Date
JP861380A Pending JPS56105653A (en) 1980-01-28 1980-01-28 Gold bump forming method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56105653A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6442842A (en) * 1987-08-10 1989-02-15 Nec Corp Manufacture of semiconductor device
US5665639A (en) * 1994-02-23 1997-09-09 Cypress Semiconductor Corp. Process for manufacturing a semiconductor device bump electrode using a rapid thermal anneal
WO2005053012A1 (en) * 2003-11-29 2005-06-09 Infineon Technologies Ag Method for galvanising and forming a contact boss

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6442842A (en) * 1987-08-10 1989-02-15 Nec Corp Manufacture of semiconductor device
US5665639A (en) * 1994-02-23 1997-09-09 Cypress Semiconductor Corp. Process for manufacturing a semiconductor device bump electrode using a rapid thermal anneal
WO2005053012A1 (en) * 2003-11-29 2005-06-09 Infineon Technologies Ag Method for galvanising and forming a contact boss

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