JPS56111191A - Read only memory device - Google Patents
Read only memory deviceInfo
- Publication number
- JPS56111191A JPS56111191A JP1315380A JP1315380A JPS56111191A JP S56111191 A JPS56111191 A JP S56111191A JP 1315380 A JP1315380 A JP 1315380A JP 1315380 A JP1315380 A JP 1315380A JP S56111191 A JPS56111191 A JP S56111191A
- Authority
- JP
- Japan
- Prior art keywords
- mosfets
- fets
- lines
- bit
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
- G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
- G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
- G11C17/126—Virtual ground arrays
Landscapes
- Read Only Memory (AREA)
Abstract
PURPOSE:To reduce the power consumption, by connecting the specific line of bit lines of ROM reading out the information by the presence of MOSFETs in matrix arragement to load elements. CONSTITUTION:MOSFETs 23-25 of an ROM22 are connected to bit lines 26', 26... 26'', and the gate is controlled with the Y decoder outputs 1.... Load FETs 20, 21 fed with the chip selection signal CS are connected to the lines 26', 26'', and a switching MOSFET40 to ground is connected via MOSFETs 29, 32 in X selection MOSFETs 27-33. For example, when the output 1, X selection signal Ao, and anti-A1' and A2' are selected to a high level, a current flows from an FET20 via FETs 27 of ON-state, lines 26', 26'', are respectively at low and high level, and the bit content of an ROM23 is read in via the NAND gate 34, and the total consumption current is 2.5 times the current fed to FETs 20 and 21, thus the power consumption can be decreased in comparison with 7.5 times in case of the provision of load elements every bit-line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1315380A JPS56111191A (en) | 1980-02-05 | 1980-02-05 | Read only memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1315380A JPS56111191A (en) | 1980-02-05 | 1980-02-05 | Read only memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS56111191A true JPS56111191A (en) | 1981-09-02 |
Family
ID=11825213
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1315380A Pending JPS56111191A (en) | 1980-02-05 | 1980-02-05 | Read only memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56111191A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60214499A (en) * | 1984-04-10 | 1985-10-26 | Matsushita Electric Ind Co Ltd | semiconductor equipment |
| EP0763830A3 (en) * | 1995-09-13 | 1998-10-21 | Siemens Aktiengesellschaft | Arrangement of memory cells in matrix form |
-
1980
- 1980-02-05 JP JP1315380A patent/JPS56111191A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60214499A (en) * | 1984-04-10 | 1985-10-26 | Matsushita Electric Ind Co Ltd | semiconductor equipment |
| EP0763830A3 (en) * | 1995-09-13 | 1998-10-21 | Siemens Aktiengesellschaft | Arrangement of memory cells in matrix form |
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