JPS57201064A - Semiconductor memory cell - Google Patents

Semiconductor memory cell

Info

Publication number
JPS57201064A
JPS57201064A JP56086209A JP8620981A JPS57201064A JP S57201064 A JPS57201064 A JP S57201064A JP 56086209 A JP56086209 A JP 56086209A JP 8620981 A JP8620981 A JP 8620981A JP S57201064 A JPS57201064 A JP S57201064A
Authority
JP
Japan
Prior art keywords
fet
line
memory cell
channel mos
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56086209A
Other languages
Japanese (ja)
Inventor
Kazuo Terada
Shunichi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56086209A priority Critical patent/JPS57201064A/en
Publication of JPS57201064A publication Critical patent/JPS57201064A/en
Priority to US06/830,919 priority patent/US4706107A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To increase the output signal of a semiconductor memory cell having first FET, second FET, wiring line, reading line and word line by setting the coupling capacity between the energizing electrode of the second FET and the substrate region of the second FET to the prescribed value. CONSTITUTION:In a memory cell employing MOSTr, P channel MOS is composed of P type first energizing electrode 11, a gate electrode 12, an N type substrate region 13 supplied with a reference voltage, and second energizing electrode 16 of electrically floated state. Similarly, an N channel MOS is composed of the regions 13, 14, 15, 16 and is connected to a reading line RR'. AA' line is a word line. The coupling capacity between the first energizing pole 14 of the N channel MOS and the region 16 is set to less than 80% of the entire capacity of the region 16. In this manner, the reading speed can be accelerated and the output power can be increased.
JP56086209A 1981-06-04 1981-06-04 Semiconductor memory cell Pending JPS57201064A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP56086209A JPS57201064A (en) 1981-06-04 1981-06-04 Semiconductor memory cell
US06/830,919 US4706107A (en) 1981-06-04 1986-02-20 IC memory cells with reduced alpha particle influence

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56086209A JPS57201064A (en) 1981-06-04 1981-06-04 Semiconductor memory cell

Publications (1)

Publication Number Publication Date
JPS57201064A true JPS57201064A (en) 1982-12-09

Family

ID=13880383

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56086209A Pending JPS57201064A (en) 1981-06-04 1981-06-04 Semiconductor memory cell

Country Status (1)

Country Link
JP (1) JPS57201064A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6278799A (en) * 1985-07-19 1987-04-11 テキサス　インスツルメンツ　インコ−ポレイテツド Dynamic random access memory cell

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5357777A (en) * 1976-11-04 1978-05-25 Hitachi Ltd Semiconductor memory device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5357777A (en) * 1976-11-04 1978-05-25 Hitachi Ltd Semiconductor memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6278799A (en) * 1985-07-19 1987-04-11 テキサス　インスツルメンツ　インコ−ポレイテツド Dynamic random access memory cell

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