JPS56111199A - Periodical scanning control system in memory device - Google Patents
Periodical scanning control system in memory deviceInfo
- Publication number
- JPS56111199A JPS56111199A JP1417480A JP1417480A JPS56111199A JP S56111199 A JPS56111199 A JP S56111199A JP 1417480 A JP1417480 A JP 1417480A JP 1417480 A JP1417480 A JP 1417480A JP S56111199 A JPS56111199 A JP S56111199A
- Authority
- JP
- Japan
- Prior art keywords
- period
- error
- signal
- periodic inspection
- detection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
PURPOSE:To enable the detection of error earlier without lowering the efficiency of information processing, by reducing the period of periodic inspection accompanied with error detection and returning the period through monitor to normal period after a given time. CONSTITUTION:The timing signal T1 with a given time interval is fed to a start signal generating circuit 2 via AND gate 9 and OR gate and also fed to an address counter 1 counting the address, allowing the periodic inspection of storage device at a given period. Further, with the error signal E with the production of error, the output of a NAND circuit 7 is inverted and FF4 is set to close and open the AND gates 9, 10. Thus, the timing signal T2 shorter in the time interval than the signal T1 is used in place of the signal T1 to reduce the period of periodic inspection. On the other hand, when the maximum count value of the counter 1 is counted at a maximum address calculation circuit 3, FF4 is reset via the circuit 3 to return the period to normal one, allowing to make earlier detection and processing of error without lowering the information processing efficiency.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55014174A JPS6022379B2 (en) | 1980-02-07 | 1980-02-07 | Periodic scan control method for storage devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55014174A JPS6022379B2 (en) | 1980-02-07 | 1980-02-07 | Periodic scan control method for storage devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56111199A true JPS56111199A (en) | 1981-09-02 |
| JPS6022379B2 JPS6022379B2 (en) | 1985-06-01 |
Family
ID=11853771
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55014174A Expired JPS6022379B2 (en) | 1980-02-07 | 1980-02-07 | Periodic scan control method for storage devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6022379B2 (en) |
-
1980
- 1980-02-07 JP JP55014174A patent/JPS6022379B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6022379B2 (en) | 1985-06-01 |
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