JPS56124258A - Manufacturing of semiconductor device - Google Patents

Manufacturing of semiconductor device

Info

Publication number
JPS56124258A
JPS56124258A JP2654380A JP2654380A JPS56124258A JP S56124258 A JPS56124258 A JP S56124258A JP 2654380 A JP2654380 A JP 2654380A JP 2654380 A JP2654380 A JP 2654380A JP S56124258 A JPS56124258 A JP S56124258A
Authority
JP
Japan
Prior art keywords
channel
type
constitution
drain
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2654380A
Other languages
Japanese (ja)
Inventor
Eiji Oi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2654380A priority Critical patent/JPS56124258A/en
Publication of JPS56124258A publication Critical patent/JPS56124258A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To make logic alteration by a single process, by employing depletion type on one of a pair of MOSFET channels, whose electric conduction types are reverse to each other, and 1 layer enhancement type on the other. CONSTITUTION:A P<-> layer 21, a P type and an N type channel stoppers 22 and 23 and a field oxide membrane 24 are provided on an N<-> type Si substrate 20, and gate oxide membranes 25 and 26 are formed. When phosphorus ion is channel doped, an N channel 28, which makes Q11 depletion type, is formed on the position where FETQ11 is formed, and an N channel 29, which makes Q21 1 layer enhancement type, is formed on the position where Q21 is formed. And then, a poly Si gate electrodes 30 and 31 are provided, and N<+> layers 32 and 33 and P<+> layers 34 and 35 are selectively provided. By this constitution, in Q11, it actually gives rise to a state of shortcircuit between a source and a drain by the N channel, and in Q21, the state between the source and the drain is actually turned into 'Open' by the N channel. By using this method, it is possible to exchange information on COMSROM at one channel peak.
JP2654380A 1980-03-05 1980-03-05 Manufacturing of semiconductor device Pending JPS56124258A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2654380A JPS56124258A (en) 1980-03-05 1980-03-05 Manufacturing of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2654380A JPS56124258A (en) 1980-03-05 1980-03-05 Manufacturing of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56124258A true JPS56124258A (en) 1981-09-29

Family

ID=12196410

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2654380A Pending JPS56124258A (en) 1980-03-05 1980-03-05 Manufacturing of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56124258A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6251248A (en) * 1985-08-30 1987-03-05 Toshiba Corp Manufacture of semiconductor device
US5239195A (en) * 1990-05-17 1993-08-24 Hello S.A. Mos transistor with high threshold voltage

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6251248A (en) * 1985-08-30 1987-03-05 Toshiba Corp Manufacture of semiconductor device
US5239195A (en) * 1990-05-17 1993-08-24 Hello S.A. Mos transistor with high threshold voltage

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