JPS5614345A - Interface for data transfer - Google Patents

Interface for data transfer

Info

Publication number
JPS5614345A
JPS5614345A JP8861379A JP8861379A JPS5614345A JP S5614345 A JPS5614345 A JP S5614345A JP 8861379 A JP8861379 A JP 8861379A JP 8861379 A JP8861379 A JP 8861379A JP S5614345 A JPS5614345 A JP S5614345A
Authority
JP
Japan
Prior art keywords
data
transfer
request signal
processing part
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8861379A
Other languages
Japanese (ja)
Inventor
Isao Tofuku
Tadatami Mori
Masaaki Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8861379A priority Critical patent/JPS5614345A/en
Publication of JPS5614345A publication Critical patent/JPS5614345A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To make it possible to apply this interface for data transfer to the check system and so on using a microcomputer advantageously, by transferring surely even a signal, which has a generation interval shorter than the processable interval, from the data supply part to the data processing part.
CONSTITUTION: In case that the generation interval time of the transfer request signal from data supply part 1 is shorter than the data processable interval time in data processing part 3, transfer of memory data DS in latch circuit 11 and transfer request signal FS1 is stopped because AND circuits 41 and 51 close gates due to reset of FF 31. In stead of these memory data and transfer request signal, memory data DS given to latch circuit 12 and transfer request signal FS1 given to AND circuit 52 are supplied to processing part 3. As a result, the signal of a generation interval shorter than the processable interval can be transferred surely to processing part 3 to apply this interface for data transfer to the check system and so on using a microcomputer advantageously.
COPYRIGHT: (C)1981,JPO&Japio
JP8861379A 1979-07-11 1979-07-11 Interface for data transfer Pending JPS5614345A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8861379A JPS5614345A (en) 1979-07-11 1979-07-11 Interface for data transfer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8861379A JPS5614345A (en) 1979-07-11 1979-07-11 Interface for data transfer

Publications (1)

Publication Number Publication Date
JPS5614345A true JPS5614345A (en) 1981-02-12

Family

ID=13947652

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8861379A Pending JPS5614345A (en) 1979-07-11 1979-07-11 Interface for data transfer

Country Status (1)

Country Link
JP (1) JPS5614345A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6144215U (en) * 1984-08-22 1986-03-24 日本設備工業株式会社 Dust collector for rusted pipe rehabilitation work

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6144215U (en) * 1984-08-22 1986-03-24 日本設備工業株式会社 Dust collector for rusted pipe rehabilitation work

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