JPS5615066A - Electrostatic induction type semiconductor logic circuit device - Google Patents
Electrostatic induction type semiconductor logic circuit deviceInfo
- Publication number
- JPS5615066A JPS5615066A JP9078279A JP9078279A JPS5615066A JP S5615066 A JPS5615066 A JP S5615066A JP 9078279 A JP9078279 A JP 9078279A JP 9078279 A JP9078279 A JP 9078279A JP S5615066 A JPS5615066 A JP S5615066A
- Authority
- JP
- Japan
- Prior art keywords
- type semiconductor
- region
- main surface
- electrostatic induction
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/211—Design considerations for internal polarisation
- H10D89/213—Design considerations for internal polarisation in field-effect devices
- H10D89/217—Design considerations for internal polarisation in field-effect devices comprising arrangements for charge injection in static induction transistor logic [SITL] devices
Landscapes
- Bipolar Transistors (AREA)
- Junction Field-Effect Transistors (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To carry out the improvement in the integrating degree of the electrostatic induction type semiconductor logic circuit device made of longitudinal bipolar transistors and junction type field effect transistors by disposing the bipolar transistors longitudinally. CONSTITUTION:An N-type semiconductor region 17 is formed by a selective diffusion process at predetermined portion on one main surface on a low specific resistance P-type semiconductor substrate 14. An N-type semiconductor layer 12 is formed by epitaxial growth on one main surface of the substrate 14 and the region 17. A ring-shaped P-type semiconductor region 15 is formed at predetermined interval from the substrate 14 on one main surface of the layer 12, and an N-type semiconductor region 11' isolated at predetermined interval from the region 14 and an N- type semiconductor region 16 formed in shallower depth than the region 15 at predetermined interval from the region 15 on the exposed layer 12 from the opening A of the region 15 are formed on the one main surface of the layer 12. In this manner, a PNP-type transistor 101 and an N channel junction type electrostatic induction transistor 102 are formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9078279A JPS5615066A (en) | 1979-07-16 | 1979-07-16 | Electrostatic induction type semiconductor logic circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9078279A JPS5615066A (en) | 1979-07-16 | 1979-07-16 | Electrostatic induction type semiconductor logic circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5615066A true JPS5615066A (en) | 1981-02-13 |
Family
ID=14008164
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9078279A Pending JPS5615066A (en) | 1979-07-16 | 1979-07-16 | Electrostatic induction type semiconductor logic circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5615066A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5142348A (en) * | 1989-08-16 | 1992-08-25 | Matsushita Electronics Corporation | Lateral thyristor |
-
1979
- 1979-07-16 JP JP9078279A patent/JPS5615066A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5142348A (en) * | 1989-08-16 | 1992-08-25 | Matsushita Electronics Corporation | Lateral thyristor |
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