JPS561565A - Manufacture of hybrid integrated circuit - Google Patents

Manufacture of hybrid integrated circuit

Info

Publication number
JPS561565A
JPS561565A JP7581779A JP7581779A JPS561565A JP S561565 A JPS561565 A JP S561565A JP 7581779 A JP7581779 A JP 7581779A JP 7581779 A JP7581779 A JP 7581779A JP S561565 A JPS561565 A JP S561565A
Authority
JP
Japan
Prior art keywords
solder
conductive path
film
integrated circuit
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7581779A
Other languages
Japanese (ja)
Inventor
Kiyohiko Oka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7581779A priority Critical patent/JPS561565A/en
Publication of JPS561565A publication Critical patent/JPS561565A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To perform both the reduction in size of a hybrid integrated circuit and the advantages of a soldering process by coating a protective film on the position for carrying pelletlike electronic part and a miniature conductive path, attaching beforehand solder at predetermined position, removing the protective film, and mounting electronic part. CONSTITUTION:Ta2N resistance film 2, NiCr alloy, Pd and Au laminate layer 3 are superimposed on an insulating substrate 1, pattened to become a conductive path for the layer 3 and a resistor for the film 2. A resist 4 is selectively formed, dipped in solder, and solder 5 is attached only onto the exposed conductive paths 3a, 3d. Electronic parts 6 are mounted on the path 3c excluding the resist 4, and are connected with ultrasonic bonding to the conductive path 3b and the Au wire 9. Then, external terminal 7, laminated ceramic capacitor 8 are carried on the position provided with solder 5, the substrate is placed in the furnace, the solder 5 is molten to connect therebetween. With this configuration high density hybrid IC device can be inexpensively formed.
JP7581779A 1979-06-15 1979-06-15 Manufacture of hybrid integrated circuit Pending JPS561565A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7581779A JPS561565A (en) 1979-06-15 1979-06-15 Manufacture of hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7581779A JPS561565A (en) 1979-06-15 1979-06-15 Manufacture of hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS561565A true JPS561565A (en) 1981-01-09

Family

ID=13587106

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7581779A Pending JPS561565A (en) 1979-06-15 1979-06-15 Manufacture of hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS561565A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61154152A (en) * 1984-12-21 1986-07-12 フィリップス　エレクトロニクス　ネムローゼ　フェンノートシャップ Housing for electronic apparatus
US4882839A (en) * 1988-04-22 1989-11-28 Nec Corporation Method of manufacturing multi-layered wiring substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61154152A (en) * 1984-12-21 1986-07-12 フィリップス　エレクトロニクス　ネムローゼ　フェンノートシャップ Housing for electronic apparatus
US4882839A (en) * 1988-04-22 1989-11-28 Nec Corporation Method of manufacturing multi-layered wiring substrate

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