JPS56159727A - Data transfer system - Google Patents

Data transfer system

Info

Publication number
JPS56159727A
JPS56159727A JP6336480A JP6336480A JPS56159727A JP S56159727 A JPS56159727 A JP S56159727A JP 6336480 A JP6336480 A JP 6336480A JP 6336480 A JP6336480 A JP 6336480A JP S56159727 A JPS56159727 A JP S56159727A
Authority
JP
Japan
Prior art keywords
data
circuit
register
control signal
transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6336480A
Other languages
Japanese (ja)
Inventor
Hiroyuki Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6336480A priority Critical patent/JPS56159727A/en
Publication of JPS56159727A publication Critical patent/JPS56159727A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K15/00Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To facilitate the design and manufacture of a transfer controlling circuit by simplifying the circuit by transferring processing data from a data carrying circuit, by transmitting and receiving a transfer controlling signal between a data judging and controlling circuit and a device at a data transfer destination. CONSTITUTION:A register 1i in a data carrying circuit 1 receives a clock signal C1 from a data processor and a data unit A transferred at the reception time is held. A register I0 in the circuit 1 holds data to be outputted to another processor and an output branched from the register 1i is received by the decoder circuit 5 of a data judging and controlling circuit 2 to judge whether it is printing data or control data, thereby applying the result to a register 6. Witch clock signals C2 and C3, the data of register 6 is inputted to a data selecting circuit 8 and comparing circuit 10. Then, the 1st control signal generating circuit 12 and the 2nd control signal generating circuit 11 perform the transmission and reception of a transfer control signal to and from the processor at a transfer destination through a control signal transmitting-receiving line 4, transferring processing data from the register I0.
JP6336480A 1980-05-15 1980-05-15 Data transfer system Pending JPS56159727A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6336480A JPS56159727A (en) 1980-05-15 1980-05-15 Data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6336480A JPS56159727A (en) 1980-05-15 1980-05-15 Data transfer system

Publications (1)

Publication Number Publication Date
JPS56159727A true JPS56159727A (en) 1981-12-09

Family

ID=13227136

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6336480A Pending JPS56159727A (en) 1980-05-15 1980-05-15 Data transfer system

Country Status (1)

Country Link
JP (1) JPS56159727A (en)

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