JPS5619660A - Complementary mis logic circuit - Google Patents

Complementary mis logic circuit

Info

Publication number
JPS5619660A
JPS5619660A JP9535479A JP9535479A JPS5619660A JP S5619660 A JPS5619660 A JP S5619660A JP 9535479 A JP9535479 A JP 9535479A JP 9535479 A JP9535479 A JP 9535479A JP S5619660 A JPS5619660 A JP S5619660A
Authority
JP
Japan
Prior art keywords
region
layer
type
channel
logic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9535479A
Other languages
Japanese (ja)
Other versions
JPS5937585B2 (en
Inventor
Hideki Fukuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP54095354A priority Critical patent/JPS5937585B2/en
Publication of JPS5619660A publication Critical patent/JPS5619660A/en
Publication of JPS5937585B2 publication Critical patent/JPS5937585B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To enhance the integration and to reduce the consuming electric power of the MIS transistors constituting the logic circuit by a method wherein a part of the semiconductor regions and the insulating layers of two MIS transistors are held in common. CONSTITUTION:A P-type region 33 and a P<+>-type region 34 are formed respectively in an N-type Si substrate 31 by diffusion, and an N<+>-type region 35 is provided in the region 33. Extending from the surface of a region 36 in the substrare 31 locating between the regions 33 and 34 to the surface of a region 37 in the neighboring region 33, these surfaces are covered with a united common insulating film 38, and a conductor layer 39 is formed on it. Constituting the circuit in this way, an N-channel type MIS transistor Q3 having the substrate 31 as the source, the region 35 as the drain, the region 37 as the channel, the layer 38 as the gate insulating layer and the layer 39 as the gate electrode layer, is constituted. A P-channel type MIS transistor Q4 having the region 33 as the source, the region 34 as the drain, the region 36 as the channel, the layer 38 as the insulating layer, the layer 39 as the gate electrode layer, is constituted and these transistors Q3 and Q4 are connected in the ordinary method.
JP54095354A 1979-07-26 1979-07-26 Complementary MIS logic circuit Expired JPS5937585B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54095354A JPS5937585B2 (en) 1979-07-26 1979-07-26 Complementary MIS logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54095354A JPS5937585B2 (en) 1979-07-26 1979-07-26 Complementary MIS logic circuit

Publications (2)

Publication Number Publication Date
JPS5619660A true JPS5619660A (en) 1981-02-24
JPS5937585B2 JPS5937585B2 (en) 1984-09-11

Family

ID=14135314

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54095354A Expired JPS5937585B2 (en) 1979-07-26 1979-07-26 Complementary MIS logic circuit

Country Status (1)

Country Link
JP (1) JPS5937585B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57190423A (en) * 1981-05-19 1982-11-24 Toshiba Corp Semiconductor circuit
JPS598431A (en) * 1982-07-07 1984-01-17 Hitachi Ltd Buffer circuit
JPS62150749U (en) * 1986-03-14 1987-09-24
JPS63131366A (en) * 1986-11-20 1988-06-03 Csk Corp Card reader
US5192393A (en) * 1989-05-24 1993-03-09 Hitachi, Ltd. Method for growing thin film by beam deposition and apparatus for practicing the same
US5469085A (en) * 1991-01-12 1995-11-21 Shibata; Tadashi Source follower using two pairs of NMOS and PMOS transistors
US5594372A (en) * 1989-06-02 1997-01-14 Shibata; Tadashi Source follower using NMOS and PMOS transistors

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57190423A (en) * 1981-05-19 1982-11-24 Toshiba Corp Semiconductor circuit
JPS598431A (en) * 1982-07-07 1984-01-17 Hitachi Ltd Buffer circuit
JPS62150749U (en) * 1986-03-14 1987-09-24
JPS63131366A (en) * 1986-11-20 1988-06-03 Csk Corp Card reader
US5192393A (en) * 1989-05-24 1993-03-09 Hitachi, Ltd. Method for growing thin film by beam deposition and apparatus for practicing the same
US5594372A (en) * 1989-06-02 1997-01-14 Shibata; Tadashi Source follower using NMOS and PMOS transistors
US5469085A (en) * 1991-01-12 1995-11-21 Shibata; Tadashi Source follower using two pairs of NMOS and PMOS transistors

Also Published As

Publication number Publication date
JPS5937585B2 (en) 1984-09-11

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