JPS5624638A - Data transmission system - Google Patents

Data transmission system

Info

Publication number
JPS5624638A
JPS5624638A JP10028579A JP10028579A JPS5624638A JP S5624638 A JPS5624638 A JP S5624638A JP 10028579 A JP10028579 A JP 10028579A JP 10028579 A JP10028579 A JP 10028579A JP S5624638 A JPS5624638 A JP S5624638A
Authority
JP
Japan
Prior art keywords
bit
transmission
register
case
character
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10028579A
Other languages
Japanese (ja)
Inventor
Shuichi Matsubara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10028579A priority Critical patent/JPS5624638A/en
Publication of JPS5624638A publication Critical patent/JPS5624638A/en
Pending legal-status Critical Current

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  • Communication Control (AREA)

Abstract

PURPOSE: To enhance the generality by transmitting every 4 bit two times in the case where the bit length is more than 4 bit and less than 8 bit and synthesizing it into one character data to write in the memory in the case of receiving it.
CONSTITUTION: 1 character (8 bit) is read to the register 2 from the memory 1, then the bit length is judged 3. In the case where the transmitted bit length is less than 8 bit and more than 4 bit, by 4 bit control module 4, 1 character is divided into the upper 4 bit and the lower 4 bit through 4 bit masking processing. Then, in the bit division module 6, as the effective data bit 4 bit, the upper 4 bit and the lower 4 bit are transmitted two times. That is, the upper 4 bit is transferred to the transmission register 7 and with respect to the transmission control mechanism 8, the transmission order is emitted, then, when the transmission interruption is returned, similarly to the upper 4 bit, the lower 4 bit is transferred to the register 7 and the transmission command is emitted to the mechanism 8.
COPYRIGHT: (C)1981,JPO&Japio
JP10028579A 1979-08-08 1979-08-08 Data transmission system Pending JPS5624638A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10028579A JPS5624638A (en) 1979-08-08 1979-08-08 Data transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10028579A JPS5624638A (en) 1979-08-08 1979-08-08 Data transmission system

Publications (1)

Publication Number Publication Date
JPS5624638A true JPS5624638A (en) 1981-03-09

Family

ID=14269911

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10028579A Pending JPS5624638A (en) 1979-08-08 1979-08-08 Data transmission system

Country Status (1)

Country Link
JP (1) JPS5624638A (en)

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