JPS5629892A - Clear control circuit - Google Patents

Clear control circuit

Info

Publication number
JPS5629892A
JPS5629892A JP10423179A JP10423179A JPS5629892A JP S5629892 A JPS5629892 A JP S5629892A JP 10423179 A JP10423179 A JP 10423179A JP 10423179 A JP10423179 A JP 10423179A JP S5629892 A JPS5629892 A JP S5629892A
Authority
JP
Japan
Prior art keywords
register
clear
stage
clock
fed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10423179A
Other languages
Japanese (ja)
Other versions
JPS6224880B2 (en
Inventor
Tomoji Nukiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10423179A priority Critical patent/JPS5629892A/en
Publication of JPS5629892A publication Critical patent/JPS5629892A/en
Publication of JPS6224880B2 publication Critical patent/JPS6224880B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers

Landscapes

  • Shift Register Type Memory (AREA)

Abstract

PURPOSE:To enable high speed clear without adding special clear function, by the shift clock control, in the shift register. CONSTITUTION:Data is read in the first stage half bit register of the one bit shift register 10 of each stage of the N stage shift register with the clock phi1 from the input terminal 2. The data is fixed to the next stage half bit register of the register 10 with the succeeding clock phi2, and as far as the clear signal is not fed from the terminal 4, the input data is sequentially shifted. When the clear signal is fed from the terminal 4, the clock phi1 is fed to the two half bit registers constituting the register 10 via the NAND circuit 9, AND circuits 6, 7 and OR circuit 8, allowing to conduct each stage of registers. Accordingly, without adding special clear circuit, high speed clear can be made with the control of shift clock.
JP10423179A 1979-08-15 1979-08-15 Clear control circuit Granted JPS5629892A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10423179A JPS5629892A (en) 1979-08-15 1979-08-15 Clear control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10423179A JPS5629892A (en) 1979-08-15 1979-08-15 Clear control circuit

Publications (2)

Publication Number Publication Date
JPS5629892A true JPS5629892A (en) 1981-03-25
JPS6224880B2 JPS6224880B2 (en) 1987-05-30

Family

ID=14375182

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10423179A Granted JPS5629892A (en) 1979-08-15 1979-08-15 Clear control circuit

Country Status (1)

Country Link
JP (1) JPS5629892A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62105638U (en) * 1985-12-20 1987-07-06

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62105638U (en) * 1985-12-20 1987-07-06

Also Published As

Publication number Publication date
JPS6224880B2 (en) 1987-05-30

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