JPS6486271A - Accumulator - Google Patents

Accumulator

Info

Publication number
JPS6486271A
JPS6486271A JP24348787A JP24348787A JPS6486271A JP S6486271 A JPS6486271 A JP S6486271A JP 24348787 A JP24348787 A JP 24348787A JP 24348787 A JP24348787 A JP 24348787A JP S6486271 A JPS6486271 A JP S6486271A
Authority
JP
Japan
Prior art keywords
supplied
adding circuit
registers
full
carrying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24348787A
Other languages
Japanese (ja)
Other versions
JP2629737B2 (en
Inventor
Takao Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP24348787A priority Critical patent/JP2629737B2/en
Publication of JPS6486271A publication Critical patent/JPS6486271A/en
Application granted granted Critical
Publication of JP2629737B2 publication Critical patent/JP2629737B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To improve an operating speed at a comulating time by executing comulation with returning adding and carrying outputs from a full adding circuit through registers, inputting these outputs to a carrying adding circuit and obtaining a comulating output. CONSTITUTION:The arbitrary bit of a value X to be successively supplied is supplied to one input edge A of full-adding circuit 1. An adding output S of this full-adding circuit 1 and a carrying output CO are respectively supplied to registers 2 and 3. A signal from the register 2 is supplied to another input edge of the full-adding circuit 1 and a signal from the register 3 is sent to one bit higher order. Then, a signal from one bit lower order is supplied to a carrying input edge CI of the full-adding circuit 1. Further, the signals from the registers 2 and 3 are supplied to registers 4 and 5 and the signals from these registers are supplied to a carrying adding circuit 6.
JP24348787A 1987-09-28 1987-09-28 accumulator Expired - Lifetime JP2629737B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24348787A JP2629737B2 (en) 1987-09-28 1987-09-28 accumulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24348787A JP2629737B2 (en) 1987-09-28 1987-09-28 accumulator

Publications (2)

Publication Number Publication Date
JPS6486271A true JPS6486271A (en) 1989-03-30
JP2629737B2 JP2629737B2 (en) 1997-07-16

Family

ID=17104619

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24348787A Expired - Lifetime JP2629737B2 (en) 1987-09-28 1987-09-28 accumulator

Country Status (1)

Country Link
JP (1) JP2629737B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001059345A1 (en) * 2000-02-14 2001-08-16 Ramon Soler Fornt Sanitary faucet

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001059345A1 (en) * 2000-02-14 2001-08-16 Ramon Soler Fornt Sanitary faucet

Also Published As

Publication number Publication date
JP2629737B2 (en) 1997-07-16

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