JPS5636725A - Initialization system of nonvolatile memory - Google Patents

Initialization system of nonvolatile memory

Info

Publication number
JPS5636725A
JPS5636725A JP11240679A JP11240679A JPS5636725A JP S5636725 A JPS5636725 A JP S5636725A JP 11240679 A JP11240679 A JP 11240679A JP 11240679 A JP11240679 A JP 11240679A JP S5636725 A JPS5636725 A JP S5636725A
Authority
JP
Japan
Prior art keywords
cpu1
power source
electric power
memory
abnormal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11240679A
Other languages
Japanese (ja)
Inventor
Kazuhiro Iwata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11240679A priority Critical patent/JPS5636725A/en
Publication of JPS5636725A publication Critical patent/JPS5636725A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent the generation of an error by preforming initialization that invalidates the contents of a nonvolatile memory in case that a backup electric power source is abnormal.
CONSTITUTION: Unless an abnormal signal is sent from backup electric power source 3, for example, to signal line 6 when the operation between CPU1 and memory 2 is actuated by turning on the electric power source, initializing circuit 4 never operates and CPU1 reads the contents of memory 2 to start the processing. When the abnormal signal is sent from backup electric power source 3 to line 6, initializing circuit 4 operates to initialize memory 2 through line 7. Therefore, CPU1 never operates in this case. Then, starting CPU1 with a program loaded never causes abnormal operation.
COPYRIGHT: (C)1981,JPO&Japio
JP11240679A 1979-09-04 1979-09-04 Initialization system of nonvolatile memory Pending JPS5636725A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11240679A JPS5636725A (en) 1979-09-04 1979-09-04 Initialization system of nonvolatile memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11240679A JPS5636725A (en) 1979-09-04 1979-09-04 Initialization system of nonvolatile memory

Publications (1)

Publication Number Publication Date
JPS5636725A true JPS5636725A (en) 1981-04-10

Family

ID=14585847

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11240679A Pending JPS5636725A (en) 1979-09-04 1979-09-04 Initialization system of nonvolatile memory

Country Status (1)

Country Link
JP (1) JPS5636725A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5432840U (en) * 1977-08-09 1979-03-03
JPS5471233U (en) * 1977-10-28 1979-05-21

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5432840U (en) * 1977-08-09 1979-03-03
JPS5471233U (en) * 1977-10-28 1979-05-21

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