JPS5580158A - False fault generation control system - Google Patents

False fault generation control system

Info

Publication number
JPS5580158A
JPS5580158A JP15404378A JP15404378A JPS5580158A JP S5580158 A JPS5580158 A JP S5580158A JP 15404378 A JP15404378 A JP 15404378A JP 15404378 A JP15404378 A JP 15404378A JP S5580158 A JPS5580158 A JP S5580158A
Authority
JP
Japan
Prior art keywords
false fault
instruction
timing
register
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15404378A
Other languages
Japanese (ja)
Other versions
JPS6022772B2 (en
Inventor
Mitsuari Shirata
Junji Miyagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP53154043A priority Critical patent/JPS6022772B2/en
Publication of JPS5580158A publication Critical patent/JPS5580158A/en
Publication of JPS6022772B2 publication Critical patent/JPS6022772B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To change arbitrarily a false fault generation position, a timing, etc., without treatments such as insertion of a special instruction into an operating program by utilizing the processing function of a sub-processing unit to control false fault generation.
CONSTITUTION: An instruction address, an address which designated the set position of a false fault, and data which sets the generation timing of the false fault are set to data processing unit 1, and the instruction address to generate the false fault and the generation timing are held in stop address register 12 and timing data register 13 respectively. Independent storage program-type system control unit 2 is connected to this unit 1 through interface 15 to SMP, and the processing function of unit 2 is used to compare the false fault generation timing set in register 13 with the timing of an executing instruction by address comparator circuit 5 when unit 1 is executing the instruction of instruction address register 3, and a false fault signal is generated in a position designated by register 13.
COPYRIGHT: (C)1980,JPO&Japio
JP53154043A 1978-12-12 1978-12-12 Simulated failure control method Expired JPS6022772B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53154043A JPS6022772B2 (en) 1978-12-12 1978-12-12 Simulated failure control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53154043A JPS6022772B2 (en) 1978-12-12 1978-12-12 Simulated failure control method

Publications (2)

Publication Number Publication Date
JPS5580158A true JPS5580158A (en) 1980-06-17
JPS6022772B2 JPS6022772B2 (en) 1985-06-04

Family

ID=15575664

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53154043A Expired JPS6022772B2 (en) 1978-12-12 1978-12-12 Simulated failure control method

Country Status (1)

Country Link
JP (1) JPS6022772B2 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS584460A (en) * 1981-06-30 1983-01-11 Fujitsu Ltd Automatic verifying device for program
JPS5916055A (en) * 1982-07-16 1984-01-27 Nec Corp Automatic generator for artificial fault
JPS5953948A (en) * 1982-09-20 1984-03-28 Fujitsu Ltd Testing circuit of information error detecting circuit
JPS6010350A (en) * 1983-06-30 1985-01-19 Fujitsu Ltd Test equipment of error processing function of computer
JPS6017542A (en) * 1983-07-08 1985-01-29 Japanese National Railways<Jnr> Fault injection device
JPS60100233A (en) * 1983-11-04 1985-06-04 Nec Corp Artificial fault generator
JPS60222936A (en) * 1984-04-20 1985-11-07 Fujitsu Ltd Diagnostic system for check circuit
JPS60239838A (en) * 1984-05-15 1985-11-28 Nec Corp False fault generator
JPS60239839A (en) * 1984-05-15 1985-11-28 Nec Corp False fault generator

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS584460A (en) * 1981-06-30 1983-01-11 Fujitsu Ltd Automatic verifying device for program
JPS5916055A (en) * 1982-07-16 1984-01-27 Nec Corp Automatic generator for artificial fault
JPS5953948A (en) * 1982-09-20 1984-03-28 Fujitsu Ltd Testing circuit of information error detecting circuit
JPS6010350A (en) * 1983-06-30 1985-01-19 Fujitsu Ltd Test equipment of error processing function of computer
JPS6017542A (en) * 1983-07-08 1985-01-29 Japanese National Railways<Jnr> Fault injection device
JPS60100233A (en) * 1983-11-04 1985-06-04 Nec Corp Artificial fault generator
JPS60222936A (en) * 1984-04-20 1985-11-07 Fujitsu Ltd Diagnostic system for check circuit
JPS60239838A (en) * 1984-05-15 1985-11-28 Nec Corp False fault generator
JPS60239839A (en) * 1984-05-15 1985-11-28 Nec Corp False fault generator

Also Published As

Publication number Publication date
JPS6022772B2 (en) 1985-06-04

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