JPS5638648A - Test input circuit - Google Patents

Test input circuit

Info

Publication number
JPS5638648A
JPS5638648A JP11502679A JP11502679A JPS5638648A JP S5638648 A JPS5638648 A JP S5638648A JP 11502679 A JP11502679 A JP 11502679A JP 11502679 A JP11502679 A JP 11502679A JP S5638648 A JPS5638648 A JP S5638648A
Authority
JP
Japan
Prior art keywords
system reset
output
priority
reset signal
test circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11502679A
Other languages
Japanese (ja)
Inventor
Akira Takai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11502679A priority Critical patent/JPS5638648A/en
Publication of JPS5638648A publication Critical patent/JPS5638648A/en
Pending legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To save the test terminal for exclusive use, by giving the priority FF driven with the output signal at the output port in which the output level is decided with the system reset signal, as the means operating the test circuit of logic integrating circuit.
CONSTITUTION: When the system reset signal is fed to the system reset input terminal 1, FF8 and priority FF14 of the output port 10 are set. Although the test circuit is operated with the output of the priority FF, since the set output is held even after the system reset signal is absent, no test circuit is operative and the system normally operates. On the other hand, when the system reset signal is given, if the external terminal 11 of the output port is O compulsively, AND condition is established between it and the signal delaying the system reset signal for a given bit, priority FF is reset and the test circuit is operated.
COPYRIGHT: (C)1981,JPO&Japio
JP11502679A 1979-09-07 1979-09-07 Test input circuit Pending JPS5638648A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11502679A JPS5638648A (en) 1979-09-07 1979-09-07 Test input circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11502679A JPS5638648A (en) 1979-09-07 1979-09-07 Test input circuit

Publications (1)

Publication Number Publication Date
JPS5638648A true JPS5638648A (en) 1981-04-13

Family

ID=14652377

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11502679A Pending JPS5638648A (en) 1979-09-07 1979-09-07 Test input circuit

Country Status (1)

Country Link
JP (1) JPS5638648A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH021031A (en) * 1988-06-02 1990-01-05 Matsushita Electric Ind Co Ltd Arithmetic processing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH021031A (en) * 1988-06-02 1990-01-05 Matsushita Electric Ind Co Ltd Arithmetic processing device

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