JPS564260A - Electronic device - Google Patents

Electronic device

Info

Publication number
JPS564260A
JPS564260A JP7920479A JP7920479A JPS564260A JP S564260 A JPS564260 A JP S564260A JP 7920479 A JP7920479 A JP 7920479A JP 7920479 A JP7920479 A JP 7920479A JP S564260 A JPS564260 A JP S564260A
Authority
JP
Japan
Prior art keywords
lead
tab
cross
resin
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7920479A
Other languages
Japanese (ja)
Inventor
Hiromichi Suzuki
Susumu Okikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7920479A priority Critical patent/JPS564260A/en
Publication of JPS564260A publication Critical patent/JPS564260A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/424—Cross-sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To improve the transfer of generated heat to a package sealed up with resin, by shaping the cross section of a tab hanger lead constituting a lead frame and the cross section of a lead on a part sealed up with resin, as U or V to increase the effective cross-sectional area. CONSTITUTION:A lead frame is composed of a tab 10 whereon a semiconductor pellet 16 is mounted, a tab hanger lead 8, an electrode lead 9, etc. The lead 9 is connected through a coupling wire 15 to the pad 14 of the pellet 16 secured on the tab 10 and is sealed up with resin to manufacture an electronic device to make a package. Flat flanges 13 are provided on the top of each of the leads 8, 9. The cross section of each lead is shaped as U or V. The tab 10 and the bottom of each lead are located at the same height. The flanges 13 are located higher than the tab 10. As a result, heat from the pellet 16 is efficiently transferred to the package and the wires 15 are located so high that a short circuit or the like does not occur.
JP7920479A 1979-06-25 1979-06-25 Electronic device Pending JPS564260A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7920479A JPS564260A (en) 1979-06-25 1979-06-25 Electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7920479A JPS564260A (en) 1979-06-25 1979-06-25 Electronic device

Publications (1)

Publication Number Publication Date
JPS564260A true JPS564260A (en) 1981-01-17

Family

ID=13683413

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7920479A Pending JPS564260A (en) 1979-06-25 1979-06-25 Electronic device

Country Status (1)

Country Link
JP (1) JPS564260A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05261516A (en) * 1992-03-13 1993-10-12 Agency Of Ind Science & Technol Gas pressure casting method of active metal
EP0587112A1 (en) * 1992-09-09 1994-03-16 Texas Instruments Incorporated Reduced capacitance lead frame for lead on chip package
WO2025075097A1 (en) * 2023-10-04 2025-04-10 ローム株式会社 Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5245261A (en) * 1975-10-08 1977-04-09 Hitachi Ltd Electronic parts

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5245261A (en) * 1975-10-08 1977-04-09 Hitachi Ltd Electronic parts

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05261516A (en) * 1992-03-13 1993-10-12 Agency Of Ind Science & Technol Gas pressure casting method of active metal
EP0587112A1 (en) * 1992-09-09 1994-03-16 Texas Instruments Incorporated Reduced capacitance lead frame for lead on chip package
US5521426A (en) * 1992-09-09 1996-05-28 Texas Instruments Incorporated Reduced capacitance lead frame for lead on chip package
WO2025075097A1 (en) * 2023-10-04 2025-04-10 ローム株式会社 Semiconductor device

Similar Documents

Publication Publication Date Title
JPS564260A (en) Electronic device
JPS57155758A (en) Semiconductor device
JPS5651851A (en) Semiconductor device
JPS5763850A (en) Semiconductor device
JPS5449066A (en) Semiconductor device
JPS57104235A (en) Semiconductor device
JPS54140465A (en) Lead frame
JPS5779629A (en) Integrated circuit device
JPS5788752A (en) Lead frame and semiconductor device prepared by using the same
JPS5617047A (en) Semiconductor device
JPS6464347A (en) Semiconductor integrated circuit
JPS5348463A (en) Semiconductor integrated circuit support
JPS55107251A (en) Electronic part and its packaging construction
JPS57111054A (en) Semiconductor device
JPS647645A (en) Semiconductor device and manufacture thereof
JPS5571051A (en) Semiconductor device
JPS57184226A (en) Semiconductor device
JPS5624959A (en) Semiconductor lead frame
JPS5637658A (en) Semiconductor device
JPS5662346A (en) Lead frame and semicondcutor device having thereof
JPS547272A (en) Semiconductor package
JPS5726459A (en) Glass-sealed semiconductor device
JPS57211284A (en) Lead frame for semiconductor device
JPS55108755A (en) Resin seal type semiconductor device
JPS5240974A (en) Package for semiconductor chips