JPS5779629A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPS5779629A JPS5779629A JP55156361A JP15636180A JPS5779629A JP S5779629 A JPS5779629 A JP S5779629A JP 55156361 A JP55156361 A JP 55156361A JP 15636180 A JP15636180 A JP 15636180A JP S5779629 A JPS5779629 A JP S5779629A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- integrated circuit
- circuit device
- chip
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
- H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
Landscapes
- Wire Bonding (AREA)
Abstract
PURPOSE:To prevent generation of mutual contact between bonding wires of an integrated circuit device by a method wherein straight lines connecting respectively the bonding part of an electrode and a bonding pad of semiconductor chip are made so as not to be piled up. CONSTITUTION:The bonding pads 22 and the electrodes 23, 24 are arranged as the straight lines connecting the bonding parts on the bonding pads 22 of the chip 20 and the bonding parts 26 on the electrodes 23, 24 of a package are made as to be converged to the center O of the chip 20. Accordingly, because the bonding wires 21 are extended toward the outside circumference of the integrated circuit device, short-circuit to be generated by mutual contact is not generated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55156361A JPS5779629A (en) | 1980-11-06 | 1980-11-06 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55156361A JPS5779629A (en) | 1980-11-06 | 1980-11-06 | Integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5779629A true JPS5779629A (en) | 1982-05-18 |
Family
ID=15626071
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55156361A Pending JPS5779629A (en) | 1980-11-06 | 1980-11-06 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5779629A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60138931A (en) * | 1983-12-27 | 1985-07-23 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JPH0348230U (en) * | 1989-09-16 | 1991-05-08 |
-
1980
- 1980-11-06 JP JP55156361A patent/JPS5779629A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60138931A (en) * | 1983-12-27 | 1985-07-23 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JPH0348230U (en) * | 1989-09-16 | 1991-05-08 |
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