JPS5642834A - Key input device - Google Patents

Key input device

Info

Publication number
JPS5642834A
JPS5642834A JP11819479A JP11819479A JPS5642834A JP S5642834 A JPS5642834 A JP S5642834A JP 11819479 A JP11819479 A JP 11819479A JP 11819479 A JP11819479 A JP 11819479A JP S5642834 A JPS5642834 A JP S5642834A
Authority
JP
Japan
Prior art keywords
error
key input
register
arithmetic
execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11819479A
Other languages
Japanese (ja)
Inventor
Hisao Nagata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11819479A priority Critical patent/JPS5642834A/en
Publication of JPS5642834A publication Critical patent/JPS5642834A/en
Pending legal-status Critical Current

Links

Landscapes

  • Calculators And Similar Devices (AREA)
  • Input From Keyboards Or The Like (AREA)

Abstract

PURPOSE: To ensure the operation of a computer regardless of the arithmetic error for the key input device of an electronic desk computer incorporating a printer, by securing an execution of the function at the time point of the key input with receiving no effect of the conditions of the error or the like.
CONSTITUTION: The output 21 given from the key input buffer register 2 is processed by the arithmetic control system comprising the arithmetic control circuit 31, the arithmetic circuit 32 and the register 33. And the print data 34 which is the output of the above process is printed by the printer 42 which is controlled by the print control circuit 41. Then the error signal 35 caused by the error occurred under operation, the overflow of the register 2 and other factors lights up the error display 5 to be then read into the register 2. Here the data receiving an effect during the execution is added to the key input data and then stored in the register 2, and the execution is carried out by referring to the data added with processing of the key input data. As a result, no effect of the conditions of the error or the like is given during the execution, thus securing an operation of the computer regardless of the arithmetic error.
COPYRIGHT: (C)1981,JPO&Japio
JP11819479A 1979-09-14 1979-09-14 Key input device Pending JPS5642834A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11819479A JPS5642834A (en) 1979-09-14 1979-09-14 Key input device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11819479A JPS5642834A (en) 1979-09-14 1979-09-14 Key input device

Publications (1)

Publication Number Publication Date
JPS5642834A true JPS5642834A (en) 1981-04-21

Family

ID=14730483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11819479A Pending JPS5642834A (en) 1979-09-14 1979-09-14 Key input device

Country Status (1)

Country Link
JP (1) JPS5642834A (en)

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