JPS5643749A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPS5643749A
JPS5643749A JP11882179A JP11882179A JPS5643749A JP S5643749 A JPS5643749 A JP S5643749A JP 11882179 A JP11882179 A JP 11882179A JP 11882179 A JP11882179 A JP 11882179A JP S5643749 A JPS5643749 A JP S5643749A
Authority
JP
Japan
Prior art keywords
resistor
hole
diffusion
resistance
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11882179A
Other languages
Japanese (ja)
Inventor
Takao Yano
Shinichiro Yamada
Takeshi Ogura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP11882179A priority Critical patent/JPS5643749A/en
Publication of JPS5643749A publication Critical patent/JPS5643749A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To manufacture the semiconductor device with a resistor in a mask pattern of a small area and in few processes by a method wherein a polycrystalline silicon in the same layer is formed as the high resistor and wiring (containing a gate), and components in the longitudinal direction are used as resistance. CONSTITUTION:A through hole 4 is made up to a thin oxide film 3 built up on a substrate 1. A diffusion layer 14 is formed into the substrate under the through hole 4, and used as one electrode of a resistor. The high resistance polycrystalline silicon 5 is made up, the region where high resistance must be left is masked, the second diffusion process is conducted, and the source and drain diffusion layers 7 of an MOS, etc. are built up. The wiring 10 is formed which is communicated with a through hole 9 just above an interphase insulating layers 8 and the resistor 5. According to the said constitution, since the resistant region is obtained in the longitudinal direction, an electrode under the resistor can be made up by means of diffusion, resistance value can also be decided according to the dimensions of the through hole 9, and the area of a mask pattern can also be made small.
JP11882179A 1979-09-18 1979-09-18 Semiconductor device and its manufacture Pending JPS5643749A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11882179A JPS5643749A (en) 1979-09-18 1979-09-18 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11882179A JPS5643749A (en) 1979-09-18 1979-09-18 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPS5643749A true JPS5643749A (en) 1981-04-22

Family

ID=14745970

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11882179A Pending JPS5643749A (en) 1979-09-18 1979-09-18 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPS5643749A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58135662A (en) * 1982-02-08 1983-08-12 Seiko Epson Corp Integrated circuit
JPS63268258A (en) * 1987-04-24 1988-11-04 Nec Corp Semiconductor device
JPS6421947A (en) * 1987-07-16 1989-01-25 Nec Corp Input protective circuit device
JPS6441558U (en) * 1987-09-03 1989-03-13
US4830976A (en) * 1984-10-01 1989-05-16 American Telephone And Telegraph Company, At&T Bell Laboratories Integrated circuit resistor
US5177030A (en) * 1991-07-03 1993-01-05 Micron Technology, Inc. Method of making self-aligned vertical intrinsic resistance
US5200356A (en) * 1988-07-29 1993-04-06 Sharp Kabushiki Kaisha Method of forming a static random access memory device
US5699292A (en) * 1996-01-04 1997-12-16 Micron Technology, Inc. SRAM cell employing substantially vertically elongated pull-up resistors
US5751630A (en) * 1996-08-29 1998-05-12 Micron Technology, Inc. SRAM cell employing substantially vertically elongated pull-up resistors
US5808941A (en) * 1996-01-04 1998-09-15 Micron Technology, Inc. SRAM cell employing substantially vertically elongated pull-up resistors

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51128278A (en) * 1975-04-30 1976-11-09 Sony Corp Integrated circuit with resistance element

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51128278A (en) * 1975-04-30 1976-11-09 Sony Corp Integrated circuit with resistance element

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58135662A (en) * 1982-02-08 1983-08-12 Seiko Epson Corp Integrated circuit
US4830976A (en) * 1984-10-01 1989-05-16 American Telephone And Telegraph Company, At&T Bell Laboratories Integrated circuit resistor
JPS63268258A (en) * 1987-04-24 1988-11-04 Nec Corp Semiconductor device
JPS6421947A (en) * 1987-07-16 1989-01-25 Nec Corp Input protective circuit device
JPS6441558U (en) * 1987-09-03 1989-03-13
US5200356A (en) * 1988-07-29 1993-04-06 Sharp Kabushiki Kaisha Method of forming a static random access memory device
US5177030A (en) * 1991-07-03 1993-01-05 Micron Technology, Inc. Method of making self-aligned vertical intrinsic resistance
US5732023A (en) * 1996-01-04 1998-03-24 Micron Technology, Inc. SRAM cell employing substantially vertically elongated pull-up resistors
US5699292A (en) * 1996-01-04 1997-12-16 Micron Technology, Inc. SRAM cell employing substantially vertically elongated pull-up resistors
US5808941A (en) * 1996-01-04 1998-09-15 Micron Technology, Inc. SRAM cell employing substantially vertically elongated pull-up resistors
US5844838A (en) * 1996-01-04 1998-12-01 Micron Technology, Inc. SRAM cell employing substantially vertically elongated pull-up resistors
US5844835A (en) * 1996-01-04 1998-12-01 Micron Technology, Inc. SCRAM cell employing substantially vertically elongated pull-up resistors
US5943269A (en) * 1996-01-04 1999-08-24 Micron Technology, Inc. SRAM cell employing substantially vertically elongated pull-up resistors
US5969994A (en) * 1996-01-04 1999-10-19 Micron Technology, Inc. Sram cell employing substantially vertically elongated pull-up resistors
US5995411A (en) * 1996-01-04 1999-11-30 Micron Technology, Inc. SRAM cell employing substantially vertically elongated pull-up resistors
US5751630A (en) * 1996-08-29 1998-05-12 Micron Technology, Inc. SRAM cell employing substantially vertically elongated pull-up resistors

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