JPS5648151A - Wiring formation of semiconductor device - Google Patents

Wiring formation of semiconductor device

Info

Publication number
JPS5648151A
JPS5648151A JP12358479A JP12358479A JPS5648151A JP S5648151 A JPS5648151 A JP S5648151A JP 12358479 A JP12358479 A JP 12358479A JP 12358479 A JP12358479 A JP 12358479A JP S5648151 A JPS5648151 A JP S5648151A
Authority
JP
Japan
Prior art keywords
wiring
layers
wiring pattern
flaws
metal wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12358479A
Other languages
Japanese (ja)
Inventor
Kimiyoshi Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12358479A priority Critical patent/JPS5648151A/en
Publication of JPS5648151A publication Critical patent/JPS5648151A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To easily obtain high density wiring by forming the second independent wiring pattern at the same plane level with the first wiring pattern by a self-matching method. CONSTITUTION:The first metal wiring layers 3 are placed on the oxide film 2 of an Si substrate 1. With resist masks 4 applied for photo etching, flaws will follow as the sides of the wiring layers are etched. With the second metal wiring layers 5 placed on the oxide film 2, intervals between the layers 3 and the layers 5 are automatically secured due to the flaws. A resist mask 6 is applied after removing the resists 4 to selectively eliminate unnecessary wires 3, 5. Next, the wires 3, 5 are covered with an insulating film 7 to form the third metal wiring layer 8 by opening the insulating film 7. In this composition, a wiring pattern having higher density of about 1.4 times than conventional multilayer wiring will be formed though a conventional photo etching technique is utilized.
JP12358479A 1979-09-26 1979-09-26 Wiring formation of semiconductor device Pending JPS5648151A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12358479A JPS5648151A (en) 1979-09-26 1979-09-26 Wiring formation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12358479A JPS5648151A (en) 1979-09-26 1979-09-26 Wiring formation of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5648151A true JPS5648151A (en) 1981-05-01

Family

ID=14864200

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12358479A Pending JPS5648151A (en) 1979-09-26 1979-09-26 Wiring formation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5648151A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60144973A (en) * 1983-12-05 1985-07-31 エナージー・コンバーシヨン・デバイセス・インコーポレーテツド Shortcircuit thin film field effect transistor
JPS60164364A (en) * 1984-02-07 1985-08-27 Seiko Instr & Electronics Ltd Manufacture of thin film semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60144973A (en) * 1983-12-05 1985-07-31 エナージー・コンバーシヨン・デバイセス・インコーポレーテツド Shortcircuit thin film field effect transistor
JPS60164364A (en) * 1984-02-07 1985-08-27 Seiko Instr & Electronics Ltd Manufacture of thin film semiconductor device

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