JPS564844A - Information processor - Google Patents

Information processor

Info

Publication number
JPS564844A
JPS564844A JP7971579A JP7971579A JPS564844A JP S564844 A JPS564844 A JP S564844A JP 7971579 A JP7971579 A JP 7971579A JP 7971579 A JP7971579 A JP 7971579A JP S564844 A JPS564844 A JP S564844A
Authority
JP
Japan
Prior art keywords
instruction
fed
signal line
pseudo
interruption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7971579A
Other languages
Japanese (ja)
Other versions
JPS6149695B2 (en
Inventor
Norimasa Furukatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7971579A priority Critical patent/JPS564844A/en
Publication of JPS564844A publication Critical patent/JPS564844A/en
Publication of JPS6149695B2 publication Critical patent/JPS6149695B2/ja
Granted legal-status Critical Current

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Abstract

PURPOSE: To perform the interruption processing with good efficiency with the execution of the instruction on the way of pre-fetch without being cancelled, by producing the pseudo-instruction at the external interruption processing unit and constituting that it is fed to the instruction register for pre-fetch.
CONSTITUTION: When effective external interruption is present, the external interruption processing unit 1 forms the interruption code corresponding to the types of interruption to produce the pseud-instruction of RM-type where the instruction code section is all made to "1". The pseudo-instruction produced is connected to the instruction selection circuit 11 via the signal line (b). The display of the production of pseudo-instruction is fed to the circuit 11 via the signal line c. The instruction buffer 13 stores the instruction read out by 8 words in parallel via the signal line (e) from the cash 6. The output of the buffer 13 is selected every one instruction and fed to the circuit 11 via the signal line (f). The instruction selected is fed to the instruction register by one instruction and fed to the instruction decoder 15 via the signal line (h).
COPYRIGHT: (C)1981,JPO&Japio
JP7971579A 1979-06-26 1979-06-26 Information processor Granted JPS564844A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7971579A JPS564844A (en) 1979-06-26 1979-06-26 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7971579A JPS564844A (en) 1979-06-26 1979-06-26 Information processor

Publications (2)

Publication Number Publication Date
JPS564844A true JPS564844A (en) 1981-01-19
JPS6149695B2 JPS6149695B2 (en) 1986-10-30

Family

ID=13697893

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7971579A Granted JPS564844A (en) 1979-06-26 1979-06-26 Information processor

Country Status (1)

Country Link
JP (1) JPS564844A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01503340A (en) * 1987-03-20 1989-11-09 ディジタル　イクイプメント　コーポレーション data processing unit
JP2009545079A (en) * 2006-07-25 2009-12-17 クゥアルコム・インコーポレイテッド Efficient interrupt return address storage mechanism

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01503340A (en) * 1987-03-20 1989-11-09 ディジタル　イクイプメント　コーポレーション data processing unit
JP2009545079A (en) * 2006-07-25 2009-12-17 クゥアルコム・インコーポレイテッド Efficient interrupt return address storage mechanism
JP2014099192A (en) * 2006-07-25 2014-05-29 Qualcomm Incorporated Efficient interrupt return address save mechanism

Also Published As

Publication number Publication date
JPS6149695B2 (en) 1986-10-30

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