JPS5644942A - Information processing unit - Google Patents

Information processing unit

Info

Publication number
JPS5644942A
JPS5644942A JP11939279A JP11939279A JPS5644942A JP S5644942 A JPS5644942 A JP S5644942A JP 11939279 A JP11939279 A JP 11939279A JP 11939279 A JP11939279 A JP 11939279A JP S5644942 A JPS5644942 A JP S5644942A
Authority
JP
Japan
Prior art keywords
instruction
loop
branch
instruction buffer
satisfied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11939279A
Other languages
Japanese (ja)
Inventor
Michihiro Hirai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11939279A priority Critical patent/JPS5644942A/en
Publication of JPS5644942A publication Critical patent/JPS5644942A/en
Pending legal-status Critical Current

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  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE: To make execution of a program loop high-speed, by giving a loop structure to the instruction buffer group as a ring counter and by closing the loop of the instruction buffer group when the program is detected.
CONSTITUTION: In case that the branch instruction enters into buffer B and it is forecasted that branch conditions are satisfied in the branch condition deciding circuit, loop deciding circuit 4 is set. Then, an instruction loop is formed only with instruction groups in the instruction buffer group. This loop forming is realized by taking the input of instruction buffer B as the output of instruction buffer C or D. Simultaneously, a loop is formed among operand address registers 6BW6D. When the branch instruction reaches the last instruction buffer, it is decided by branch deciding circuit 20 whether branch conditions are satisfied or not. As long as it is decided that branch conditions are satisfied, loops of the instruction buffer group and the operand address register group are continued.
COPYRIGHT: (C)1981,JPO&Japio
JP11939279A 1979-09-19 1979-09-19 Information processing unit Pending JPS5644942A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11939279A JPS5644942A (en) 1979-09-19 1979-09-19 Information processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11939279A JPS5644942A (en) 1979-09-19 1979-09-19 Information processing unit

Publications (1)

Publication Number Publication Date
JPS5644942A true JPS5644942A (en) 1981-04-24

Family

ID=14760359

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11939279A Pending JPS5644942A (en) 1979-09-19 1979-09-19 Information processing unit

Country Status (1)

Country Link
JP (1) JPS5644942A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59165144A (en) * 1983-03-07 1984-09-18 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Order extractor
WO2002073411A1 (en) * 2001-02-22 2002-09-19 Hitachi, Ltd Memory testing method, information recording medium, and semiconductor integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59165144A (en) * 1983-03-07 1984-09-18 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Order extractor
WO2002073411A1 (en) * 2001-02-22 2002-09-19 Hitachi, Ltd Memory testing method, information recording medium, and semiconductor integrated circuit

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