JPS5651097A - Main storage control device - Google Patents

Main storage control device

Info

Publication number
JPS5651097A
JPS5651097A JP12701579A JP12701579A JPS5651097A JP S5651097 A JPS5651097 A JP S5651097A JP 12701579 A JP12701579 A JP 12701579A JP 12701579 A JP12701579 A JP 12701579A JP S5651097 A JPS5651097 A JP S5651097A
Authority
JP
Japan
Prior art keywords
information
register
failed
bank
block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12701579A
Other languages
Japanese (ja)
Inventor
Akira Ueno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12701579A priority Critical patent/JPS5651097A/en
Publication of JPS5651097A publication Critical patent/JPS5651097A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To make unnecessary the detaching of failed memory bank and reconstitution, by splitting memory banks of independent access unit into logic blocks and performing comparison processing through the storage of the information.
CONSTITUTION: The 1st, 2nd... memory banks 9, 10... of independent access unit of a main storage device are respectively split into the 1st... logic block 13.... According to access request, the bank and logical block of the address information is set to an address register 2 and it is compared with the content of a failed information register 8 at a comparator 4. Further, if the information of the register 2 is not the information of the failed bank, the information is transferred as it is. In case of the failed bank, the block information of the register 2 and that of the register 8 are compared at a comparator 5, and if it is smaller than the block information in the register 8, the processing is made the same as no failure, and if equal or greater, the logic block information is processed with addition. Accordingly, the area possible for usage can effectively be utilized without the necessity of detaching of failed banks and reconstitution.
COPYRIGHT: (C)1981,JPO&Japio
JP12701579A 1979-10-02 1979-10-02 Main storage control device Pending JPS5651097A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12701579A JPS5651097A (en) 1979-10-02 1979-10-02 Main storage control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12701579A JPS5651097A (en) 1979-10-02 1979-10-02 Main storage control device

Publications (1)

Publication Number Publication Date
JPS5651097A true JPS5651097A (en) 1981-05-08

Family

ID=14949569

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12701579A Pending JPS5651097A (en) 1979-10-02 1979-10-02 Main storage control device

Country Status (1)

Country Link
JP (1) JPS5651097A (en)

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