JPS5651126A - Fail safe logical operation circuit - Google Patents
Fail safe logical operation circuitInfo
- Publication number
- JPS5651126A JPS5651126A JP12733879A JP12733879A JPS5651126A JP S5651126 A JPS5651126 A JP S5651126A JP 12733879 A JP12733879 A JP 12733879A JP 12733879 A JP12733879 A JP 12733879A JP S5651126 A JPS5651126 A JP S5651126A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- power source
- ttl circuit
- fail safe
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 abstract 2
- 238000005513 bias potential Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/007—Fail-safe circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To constitute a TTL circuit which has the fail safe function for the power source break fault, by connecting a resistance between the input part and the power source terminal of the receiving TTL circuit. CONSTITUTION:Output part 27 of TTL circuit 25 with transmission off-buffer circuit is connected to input part 31 of receiving TTL circuit 30, and further, pull-up resistance R1 35 is connected between input part 31 and power source terminal VCC4. By adding pull-up resistance R1, a proper bias potential can be set, and the output of the TTL circuit with the transmission off-buffer circuit for power source break is established in the logical high level, and receiving TTL circuit output 32 is established in the logical low level because of the inverter circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12733879A JPS5651126A (en) | 1979-10-04 | 1979-10-04 | Fail safe logical operation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12733879A JPS5651126A (en) | 1979-10-04 | 1979-10-04 | Fail safe logical operation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5651126A true JPS5651126A (en) | 1981-05-08 |
Family
ID=14957442
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12733879A Pending JPS5651126A (en) | 1979-10-04 | 1979-10-04 | Fail safe logical operation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5651126A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02143008A (en) * | 1988-11-25 | 1990-06-01 | Nakadai Kogyo Kk | Waste incinerator of needle and the like and their waste incineration method by the use of the incinerator |
-
1979
- 1979-10-04 JP JP12733879A patent/JPS5651126A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02143008A (en) * | 1988-11-25 | 1990-06-01 | Nakadai Kogyo Kk | Waste incinerator of needle and the like and their waste incineration method by the use of the incinerator |
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