JPS5651126A - Fail safe logical operation circuit - Google Patents

Fail safe logical operation circuit

Info

Publication number
JPS5651126A
JPS5651126A JP12733879A JP12733879A JPS5651126A JP S5651126 A JPS5651126 A JP S5651126A JP 12733879 A JP12733879 A JP 12733879A JP 12733879 A JP12733879 A JP 12733879A JP S5651126 A JPS5651126 A JP S5651126A
Authority
JP
Japan
Prior art keywords
circuit
power source
ttl circuit
fail safe
resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12733879A
Other languages
Japanese (ja)
Inventor
Masahiro Fuwa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12733879A priority Critical patent/JPS5651126A/en
Publication of JPS5651126A publication Critical patent/JPS5651126A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/007—Fail-safe circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To constitute a TTL circuit which has the fail safe function for the power source break fault, by connecting a resistance between the input part and the power source terminal of the receiving TTL circuit. CONSTITUTION:Output part 27 of TTL circuit 25 with transmission off-buffer circuit is connected to input part 31 of receiving TTL circuit 30, and further, pull-up resistance R1 35 is connected between input part 31 and power source terminal VCC4. By adding pull-up resistance R1, a proper bias potential can be set, and the output of the TTL circuit with the transmission off-buffer circuit for power source break is established in the logical high level, and receiving TTL circuit output 32 is established in the logical low level because of the inverter circuit.
JP12733879A 1979-10-04 1979-10-04 Fail safe logical operation circuit Pending JPS5651126A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12733879A JPS5651126A (en) 1979-10-04 1979-10-04 Fail safe logical operation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12733879A JPS5651126A (en) 1979-10-04 1979-10-04 Fail safe logical operation circuit

Publications (1)

Publication Number Publication Date
JPS5651126A true JPS5651126A (en) 1981-05-08

Family

ID=14957442

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12733879A Pending JPS5651126A (en) 1979-10-04 1979-10-04 Fail safe logical operation circuit

Country Status (1)

Country Link
JP (1) JPS5651126A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02143008A (en) * 1988-11-25 1990-06-01 Nakadai Kogyo Kk Waste incinerator of needle and the like and their waste incineration method by the use of the incinerator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02143008A (en) * 1988-11-25 1990-06-01 Nakadai Kogyo Kk Waste incinerator of needle and the like and their waste incineration method by the use of the incinerator

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