JPS5654132A - Automatic equalizer - Google Patents

Automatic equalizer

Info

Publication number
JPS5654132A
JPS5654132A JP13101479A JP13101479A JPS5654132A JP S5654132 A JPS5654132 A JP S5654132A JP 13101479 A JP13101479 A JP 13101479A JP 13101479 A JP13101479 A JP 13101479A JP S5654132 A JPS5654132 A JP S5654132A
Authority
JP
Japan
Prior art keywords
circuits
signal
output
equalization
adders
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13101479A
Other languages
Japanese (ja)
Other versions
JPH0159776B2 (en
Inventor
Fumio Akashi
Toru Koyama
Masaru Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13101479A priority Critical patent/JPS5654132A/en
Publication of JPS5654132A publication Critical patent/JPS5654132A/en
Publication of JPH0159776B2 publication Critical patent/JPH0159776B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Filters That Use Time-Delay Elements (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

PURPOSE:To enable equalization wide in drawing-in range, by the combination of the first adjusting means using reception signal and the second adjusting means using an identifying signal. CONSTITUTION:The reception signal incoming from a terminal 1 is output at a terminal 4 as an identifying signal via an accumulator 2 and a threshold value circuit 3. This identifying signal is subtracted with the signal of the accumulator 2 at a subtractor 15 and an error signal is made. This error signal is multiplied with the output of delay circuits 5, 6 at multipliers 16, 17 and added with the output of gain hold circuits 22, 23 at adders 20, 21 to be input to switching circuits 13, 14. The circuits 13, 14 select the output of peak detection circuits 11, 12 when the reception signal is reached, and after that, when the state of equalization is excellent, they are switched to the adders 21, 22. Further, rough control is made at the circuits 11, 12 and accurate control is made with the output of the circuit 3 afterward, allowing wide equalization of drawing-in range.
JP13101479A 1979-10-11 1979-10-11 Automatic equalizer Granted JPS5654132A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13101479A JPS5654132A (en) 1979-10-11 1979-10-11 Automatic equalizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13101479A JPS5654132A (en) 1979-10-11 1979-10-11 Automatic equalizer

Publications (2)

Publication Number Publication Date
JPS5654132A true JPS5654132A (en) 1981-05-14
JPH0159776B2 JPH0159776B2 (en) 1989-12-19

Family

ID=15047962

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13101479A Granted JPS5654132A (en) 1979-10-11 1979-10-11 Automatic equalizer

Country Status (1)

Country Link
JP (1) JPS5654132A (en)

Also Published As

Publication number Publication date
JPH0159776B2 (en) 1989-12-19

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