JPS5660948A - Signal processing system of digital logic circuit constituting closed loop - Google Patents

Signal processing system of digital logic circuit constituting closed loop

Info

Publication number
JPS5660948A
JPS5660948A JP13699379A JP13699379A JPS5660948A JP S5660948 A JPS5660948 A JP S5660948A JP 13699379 A JP13699379 A JP 13699379A JP 13699379 A JP13699379 A JP 13699379A JP S5660948 A JPS5660948 A JP S5660948A
Authority
JP
Japan
Prior art keywords
signal processing
processing
memory cell
cell group
run
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13699379A
Other languages
Japanese (ja)
Other versions
JPS6148175B2 (en
Inventor
Hirohisa Karibe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13699379A priority Critical patent/JPS5660948A/en
Publication of JPS5660948A publication Critical patent/JPS5660948A/en
Publication of JPS6148175B2 publication Critical patent/JPS6148175B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To increase the speed of processing by eliminating troubles regarding design by avoiding contention while eliminating write operation by time slots when a read by time slots is taken in some signal processing run.
CONSTITUTION: Processing result C1.S2(i-1) of small signal processing C1 in the (i-1)-th signal processing run is read out of memory cell group M1 by time slot TS1 and then processed by signal processing circuit 11, whose processing result C1.S1(i) is written in memory cell group M(m+1). Similarly, processing result S2.S2(i-1) of small signal processing C2 in the (i-1)-th signal processing run is read out of memory cell group M2 by time slot TS2 and then processed by circuit 11, whose result C2.S2(i) is written in preceding memory cell group M1. Thus, the read operation and write operation never cause contention in the same signal run, troubles regarding design are eliminated and the speed of the processing can be increased.
COPYRIGHT: (C)1981,JPO&Japio
JP13699379A 1979-10-25 1979-10-25 Signal processing system of digital logic circuit constituting closed loop Granted JPS5660948A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13699379A JPS5660948A (en) 1979-10-25 1979-10-25 Signal processing system of digital logic circuit constituting closed loop

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13699379A JPS5660948A (en) 1979-10-25 1979-10-25 Signal processing system of digital logic circuit constituting closed loop

Publications (2)

Publication Number Publication Date
JPS5660948A true JPS5660948A (en) 1981-05-26
JPS6148175B2 JPS6148175B2 (en) 1986-10-23

Family

ID=15188268

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13699379A Granted JPS5660948A (en) 1979-10-25 1979-10-25 Signal processing system of digital logic circuit constituting closed loop

Country Status (1)

Country Link
JP (1) JPS5660948A (en)

Also Published As

Publication number Publication date
JPS6148175B2 (en) 1986-10-23

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