JPS5662368A - Manufacturing of accommodation mos integrated circuit - Google Patents

Manufacturing of accommodation mos integrated circuit

Info

Publication number
JPS5662368A
JPS5662368A JP13838779A JP13838779A JPS5662368A JP S5662368 A JPS5662368 A JP S5662368A JP 13838779 A JP13838779 A JP 13838779A JP 13838779 A JP13838779 A JP 13838779A JP S5662368 A JPS5662368 A JP S5662368A
Authority
JP
Japan
Prior art keywords
base board
phospher
latch
covered
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13838779A
Other languages
Japanese (ja)
Inventor
Hiroshi Nozawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13838779A priority Critical patent/JPS5662368A/en
Publication of JPS5662368A publication Critical patent/JPS5662368A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/854—Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To provide a latch-up procedure and prevent a latch-up phenomenum after completing a high thermal process by a method wherin each of the electrodes is formed, a surface of the base board is covered with an insulation film, a getter processing is performed under a dispersion of phospher and thereafter a heavy metal for decreasing a life of carrier in the base board is dispersed from a back surface of the base board. CONSTITUTION:Source at n channel, n<+> type layers 611, 612 forming a drain, and P<+> type layers 621, 622 forming a drain are made, then all the surfaces are covered by a silicone oxide film 7, a phospher is dispersed to perform a getter processing and to remove a highly concentrated phospher glass film formed on the surface. Then, Au film 8 of about 50-200Angstrom is covered on a back surface of the base board 1, heat treated at 850 deg.C to disperse Au in the base board 1. Then, a concentration of Au in the base board 1 becomes about 10<15>/cm<2>. Then, Au dispersion is performed for latch-up procedure after all the high thermal processings are completed.
JP13838779A 1979-10-26 1979-10-26 Manufacturing of accommodation mos integrated circuit Pending JPS5662368A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13838779A JPS5662368A (en) 1979-10-26 1979-10-26 Manufacturing of accommodation mos integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13838779A JPS5662368A (en) 1979-10-26 1979-10-26 Manufacturing of accommodation mos integrated circuit

Publications (1)

Publication Number Publication Date
JPS5662368A true JPS5662368A (en) 1981-05-28

Family

ID=15220745

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13838779A Pending JPS5662368A (en) 1979-10-26 1979-10-26 Manufacturing of accommodation mos integrated circuit

Country Status (1)

Country Link
JP (1) JPS5662368A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58218173A (en) * 1982-05-10 1983-12-19 ゼネラル・エレクトリツク・カンパニイ Bidirectional power high speed mosfet element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58218173A (en) * 1982-05-10 1983-12-19 ゼネラル・エレクトリツク・カンパニイ Bidirectional power high speed mosfet element

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