JPS566522A - False irregular signal generator - Google Patents

False irregular signal generator

Info

Publication number
JPS566522A
JPS566522A JP8284679A JP8284679A JPS566522A JP S566522 A JPS566522 A JP S566522A JP 8284679 A JP8284679 A JP 8284679A JP 8284679 A JP8284679 A JP 8284679A JP S566522 A JPS566522 A JP S566522A
Authority
JP
Japan
Prior art keywords
gate
output
contents
false
shift
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8284679A
Other languages
Japanese (ja)
Inventor
Makoto Inagi
Sadanobu Ishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8284679A priority Critical patent/JPS566522A/en
Publication of JPS566522A publication Critical patent/JPS566522A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/84—Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators

Abstract

PURPOSE:To avoid all contents of each step of the shift register from turning to ''0'', by adding the gate to the false irregular signal generator of the M (maximum length cycle) series. CONSTITUTION:The contents of each step of shift registers 1-4 are supplied to N-input NOR gate 6, and then the output of gate 6 delivers ''1'' only when the contents of each step of the shift registers are all turned to ''0'' and delivers ''0'' in other cases. Accordingly, the gating is given through OR gate 7 to the output of gate 6 and the output of No. N step shown at shift register 4. As a result, the output of gate 7 becomes ''1'' when the contents of each shift-register are all ''0'' to be free from the state of ''0''. Furthermore, the output of gate 6 becomes ''0'' in case the contents of each step of registers 1-4 become free from ''0'', and thus the output of gate 7 becomes equal to the value of shift register 4 of No. N step to secure the function of the M-series generator.
JP8284679A 1979-06-28 1979-06-28 False irregular signal generator Pending JPS566522A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8284679A JPS566522A (en) 1979-06-28 1979-06-28 False irregular signal generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8284679A JPS566522A (en) 1979-06-28 1979-06-28 False irregular signal generator

Publications (1)

Publication Number Publication Date
JPS566522A true JPS566522A (en) 1981-01-23

Family

ID=13785741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8284679A Pending JPS566522A (en) 1979-06-28 1979-06-28 False irregular signal generator

Country Status (1)

Country Link
JP (1) JPS566522A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01253320A (en) * 1988-03-31 1989-10-09 Nec Corp Cyclic encoding circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01253320A (en) * 1988-03-31 1989-10-09 Nec Corp Cyclic encoding circuit

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