JPS5665384A - Information processor - Google Patents

Information processor

Info

Publication number
JPS5665384A
JPS5665384A JP14056779A JP14056779A JPS5665384A JP S5665384 A JPS5665384 A JP S5665384A JP 14056779 A JP14056779 A JP 14056779A JP 14056779 A JP14056779 A JP 14056779A JP S5665384 A JPS5665384 A JP S5665384A
Authority
JP
Japan
Prior art keywords
signal
memory
count
hit
speed buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14056779A
Other languages
Japanese (ja)
Inventor
Wataru Shimoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14056779A priority Critical patent/JPS5665384A/en
Publication of JPS5665384A publication Critical patent/JPS5665384A/en
Pending legal-status Critical Current

Links

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To calculate a HIT ratio by providing an information processing unit, equipped with a high-speed buffer memory, with a readable counter that integrating read memory requests, a readable counter that finds the frequency that read memory requests hit the high-speed buffer memory, and FF for count period control.
CONSTITUTION: When high-speed buffer memory 2 is accessed and hit by address signal 1a from a address register 1, memory signal 2a turns into 1. The 1st AND circuit 4, when three conditions of count control signal 3a, memory signal 2a and read memory request signal 6 of FF3 are satisfied, allows bit frequency integrating counter 7 to count up by one. The 2nd logic circuit 5, when two conditions of count control signal 3a and read memory request signal 6 are satisfied, allows read memory request frequency integrating counter 8 to count up by one. Outputs 7a and 8a of counters 7 and 8 are sent to data bus to calculate HIT ratios. Consequently, the HIT ratio of the high-speed buffer memory in a period when the measurement is desired can be calculated.
COPYRIGHT: (C)1981,JPO&Japio
JP14056779A 1979-10-31 1979-10-31 Information processor Pending JPS5665384A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14056779A JPS5665384A (en) 1979-10-31 1979-10-31 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14056779A JPS5665384A (en) 1979-10-31 1979-10-31 Information processor

Publications (1)

Publication Number Publication Date
JPS5665384A true JPS5665384A (en) 1981-06-03

Family

ID=15271677

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14056779A Pending JPS5665384A (en) 1979-10-31 1979-10-31 Information processor

Country Status (1)

Country Link
JP (1) JPS5665384A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS592281A (en) * 1982-06-25 1984-01-07 Nec Corp Buffer memory system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS592281A (en) * 1982-06-25 1984-01-07 Nec Corp Buffer memory system

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