JPS566541A - Semiconductor logic circuit - Google Patents

Semiconductor logic circuit

Info

Publication number
JPS566541A
JPS566541A JP8189879A JP8189879A JPS566541A JP S566541 A JPS566541 A JP S566541A JP 8189879 A JP8189879 A JP 8189879A JP 8189879 A JP8189879 A JP 8189879A JP S566541 A JPS566541 A JP S566541A
Authority
JP
Japan
Prior art keywords
minimum
channel
threshold level
beta
logic threshold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8189879A
Other languages
Japanese (ja)
Inventor
Tsutomu Iima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8189879A priority Critical patent/JPS566541A/en
Publication of JPS566541A publication Critical patent/JPS566541A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0021—Modifications of threshold
    • H03K19/0027—Modifications of threshold in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To obtain a complementary semicondcutor circuit which can shift freely the logic threshold level with the minimum the occupying area and the minimum charge/discharge power, by installing the resistance means in series to the source- drain line of at least one of p and n channel MISFET. CONSTITUTION:MISFETMN3, MP3 consisting of the minimum patterns of n and p channels constitute an inverter having input In and output OUT. And MISFETMRP for resistance functions to lower beta of the P-channel side and conducts constantly to increase the beta ratio equivalently. Thus the logic threshold level is shifted toward p channel. The beta ratio is controlled by the conductance of FETMRP. As a result, the driving FET can be made into the minimum pattern to obtain the multi-input circuit easily. In addition, the rotational design is possible in the smaller occupying area than conventional.
JP8189879A 1979-06-28 1979-06-28 Semiconductor logic circuit Pending JPS566541A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8189879A JPS566541A (en) 1979-06-28 1979-06-28 Semiconductor logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8189879A JPS566541A (en) 1979-06-28 1979-06-28 Semiconductor logic circuit

Publications (1)

Publication Number Publication Date
JPS566541A true JPS566541A (en) 1981-01-23

Family

ID=13759252

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8189879A Pending JPS566541A (en) 1979-06-28 1979-06-28 Semiconductor logic circuit

Country Status (1)

Country Link
JP (1) JPS566541A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59158129A (en) * 1983-02-28 1984-09-07 Hitachi Ltd Semiconductor integrated circuit device
JPS6062726A (en) * 1983-09-17 1985-04-10 Fujitsu Ltd C-mos inverter
JPS61172435A (en) * 1985-01-26 1986-08-04 Toshiba Corp Semiconductor integrated circuit
JPS61237515A (en) * 1985-04-12 1986-10-22 Nec Ic Microcomput Syst Ltd Inverter circuit
JPS62230220A (en) * 1986-03-31 1987-10-08 Toshiba Corp Complementary insulation gate type logic circuit
JPH0272023U (en) * 1988-11-18 1990-06-01
US5365483A (en) * 1991-05-31 1994-11-15 Thunderbird Technologies, Inc. Random access memory architecture including primary and signal bit lines and coupling means therefor
WO2009028297A1 (en) * 2007-08-31 2009-03-05 Tokyo Institute Of Technology Electronic circuit

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59158129A (en) * 1983-02-28 1984-09-07 Hitachi Ltd Semiconductor integrated circuit device
JPS6062726A (en) * 1983-09-17 1985-04-10 Fujitsu Ltd C-mos inverter
JPS61172435A (en) * 1985-01-26 1986-08-04 Toshiba Corp Semiconductor integrated circuit
JPS61237515A (en) * 1985-04-12 1986-10-22 Nec Ic Microcomput Syst Ltd Inverter circuit
JPS62230220A (en) * 1986-03-31 1987-10-08 Toshiba Corp Complementary insulation gate type logic circuit
JPH0272023U (en) * 1988-11-18 1990-06-01
US5365483A (en) * 1991-05-31 1994-11-15 Thunderbird Technologies, Inc. Random access memory architecture including primary and signal bit lines and coupling means therefor
US5388075A (en) * 1991-05-31 1995-02-07 Thunderbird Technologies, Inc. Read and write timing system for random access memory
US5396457A (en) * 1991-05-31 1995-03-07 Thunderbird Technologies, Inc. Random access memory including or gate sensing networks
US5424980A (en) * 1991-05-31 1995-06-13 Thunderbird Technologies, Inc. Self-timing random access memory
WO2009028297A1 (en) * 2007-08-31 2009-03-05 Tokyo Institute Of Technology Electronic circuit

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