JPH0272023U - - Google Patents
Info
- Publication number
- JPH0272023U JPH0272023U JP15083088U JP15083088U JPH0272023U JP H0272023 U JPH0272023 U JP H0272023U JP 15083088 U JP15083088 U JP 15083088U JP 15083088 U JP15083088 U JP 15083088U JP H0272023 U JPH0272023 U JP H0272023U
- Authority
- JP
- Japan
- Prior art keywords
- mos
- capacitor
- series
- connection point
- reset pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 1
Landscapes
- Electronic Switches (AREA)
Description
第１図は、本考案の実施例を示す回路図、第２
図は、閾値電圧とチヤンネル幅の関係を示す特性
図、第３図は、他の実施例を示す回路図、第４図
は、従来例を示す回路図である。
１，４……コンデンサ、２……Ｎ―ＭＯＳ、３
……Ｐ―ＭＯＳ、５……Ｐ―ＭＯＳ、６……Ｎ―
ＭＯＳ、７……寄生ダイオード、８……Ｎ―ＭＯ
Ｓ。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a characteristic diagram showing the relationship between threshold voltage and channel width, FIG. 3 is a circuit diagram showing another embodiment, and FIG. 4 is a circuit diagram showing a conventional example. 1, 4... Capacitor, 2... N-MOS, 3
...P-MOS, 5...P-MOS, 6...N-
MOS, 7...parasitic diode, 8...N-MO
S.
Claims (1)
ＭＯＳと、 直列接続され、前記第１のコンデンサと第１の
ＭＯＳの接続点がゲートに接続された第２のＭＯ
Ｓ及び第２のコンデンサと、 第２のＭＯＳ及び第２のコンデンサの接続点が
入力に接続されたＣ―ＭＯＳインバータと、を備
えたリセツトパスル発生回路において、 前記Ｃ―ＭＯＳインバータを構成するＮ―ＭＯ
Ｓの閾値電圧が上昇する領域のチヤンネル幅とす
ることを特徴とするリセツトパルス発生回路。 (2) 直列接続された第１のコンデンサと第１の
ＭＯＳと、 直列接続され、前記第１のコンデンサと第１の
ＭＯＳの接続点がゲートに接続された第２のＭＯ
Ｓ及び第２のコンデンサと、 第２のＭＯＳ及び第２のコンデンサの接続点が
入力に接続されたＣ―ＭＯＳインバータと、を備
えたリセツトパスル発生回路において、 前記Ｃ―ＭＯＳインバータを構成するＮ―ＭＯ
Ｓのソースと接地電圧間に少なくとも一個以上の
Ｎ―ＭＯＳを設けたことを特徴とするリセツトパ
ルス発生回路。 (3) 前記Ｃ―ＭＯＳインバータのＮ―ＭＯＳ及
び該Ｎ―ＭＯＳに接続されたＮ―ＭＯＳは同一ウ
エル内に設けられることを特徴とする請求項第２
項記載のリセツトパルス発生回路。[Claims for Utility Model Registration] (1) A first capacitor and a first MOS connected in series; 2 MO
and a C-MOS inverter whose input is connected to the connection point of the second MOS and the second capacitor; M.O.
A reset pulse generating circuit characterized in that the channel width is set to a region where the threshold voltage of S increases. (2) A first capacitor and a first MOS connected in series, and a second MO connected in series, with a connection point between the first capacitor and the first MOS connected to the gate.
and a C-MOS inverter whose input is connected to the connection point of the second MOS and the second capacitor; M.O.
A reset pulse generating circuit characterized in that at least one N-MOS is provided between the source of S and the ground voltage. (3) Claim 2, characterized in that the N-MOS of the C-MOS inverter and the N-MOS connected to the N-MOS are provided in the same well.
The reset pulse generation circuit described in .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988150830U JP2536629Y2 (en) | 1988-11-18 | 1988-11-18 | Reset pulse generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988150830U JP2536629Y2 (en) | 1988-11-18 | 1988-11-18 | Reset pulse generation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0272023U true JPH0272023U (en) | 1990-06-01 |
| JP2536629Y2 JP2536629Y2 (en) | 1997-05-21 |
Family
ID=31424323
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988150830U Expired - Lifetime JP2536629Y2 (en) | 1988-11-18 | 1988-11-18 | Reset pulse generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2536629Y2 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS566541A (en) * | 1979-06-28 | 1981-01-23 | Nec Corp | Semiconductor logic circuit |
| JPS56100515A (en) * | 1980-01-17 | 1981-08-12 | Matsushita Electric Works Ltd | Reset circuit |
| JPS6273634U (en) * | 1985-10-29 | 1987-05-12 |
-
1988
- 1988-11-18 JP JP1988150830U patent/JP2536629Y2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS566541A (en) * | 1979-06-28 | 1981-01-23 | Nec Corp | Semiconductor logic circuit |
| JPS56100515A (en) * | 1980-01-17 | 1981-08-12 | Matsushita Electric Works Ltd | Reset circuit |
| JPS6273634U (en) * | 1985-10-29 | 1987-05-12 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2536629Y2 (en) | 1997-05-21 |
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