JPS5671133A - Input circuit - Google Patents

Input circuit

Info

Publication number
JPS5671133A
JPS5671133A JP14693679A JP14693679A JPS5671133A JP S5671133 A JPS5671133 A JP S5671133A JP 14693679 A JP14693679 A JP 14693679A JP 14693679 A JP14693679 A JP 14693679A JP S5671133 A JPS5671133 A JP S5671133A
Authority
JP
Japan
Prior art keywords
outputs
flops
f1wf7
flip
gates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14693679A
Other languages
Japanese (ja)
Inventor
Kunio Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP14693679A priority Critical patent/JPS5671133A/en
Publication of JPS5671133A publication Critical patent/JPS5671133A/en
Pending legal-status Critical Current

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  • Input From Keyboards Or The Like (AREA)

Abstract

PURPOSE: To obtain the input circuit device of a simple circuit constitution where two kinds of keyboard different in character arrangement format can be switched and used, by providing a key code converting circuit.
CONSTITUTION: When any of keyboards (switches) I-1WIII-7 arranged in matrix form is depressed, the corresponding code is shown as the output of flip-flops F1W F7. When change-over switch 2 is connected to the 2-2 side, outputs of flip-flops F1WF7 are obtained as outputs of OR gates OR11WOR12 through AND gates AND11WAND17. When change-over switch 2 is connected to the 2-1 side, outputs of filp-flops F1WF7 are converted by code converting circuit 3, and the output of converter 4 becomes H-level, and therefore, they are obtained as outputs of OR circuits OR11WOR17 through AND circuits AND21WAND27.
COPYRIGHT: (C)1981,JPO&Japio
JP14693679A 1979-11-12 1979-11-12 Input circuit Pending JPS5671133A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14693679A JPS5671133A (en) 1979-11-12 1979-11-12 Input circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14693679A JPS5671133A (en) 1979-11-12 1979-11-12 Input circuit

Publications (1)

Publication Number Publication Date
JPS5671133A true JPS5671133A (en) 1981-06-13

Family

ID=15418913

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14693679A Pending JPS5671133A (en) 1979-11-12 1979-11-12 Input circuit

Country Status (1)

Country Link
JP (1) JPS5671133A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4613247A (en) * 1982-07-26 1986-09-23 Fwm Enterprises, Inc. Multiple format keyboard
JPS63168529U (en) * 1987-04-21 1988-11-02

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4613247A (en) * 1982-07-26 1986-09-23 Fwm Enterprises, Inc. Multiple format keyboard
JPS63168529U (en) * 1987-04-21 1988-11-02

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