JPS5671933A - Impurity diffusion to semiconductor substrate - Google Patents

Impurity diffusion to semiconductor substrate

Info

Publication number
JPS5671933A
JPS5671933A JP14896579A JP14896579A JPS5671933A JP S5671933 A JPS5671933 A JP S5671933A JP 14896579 A JP14896579 A JP 14896579A JP 14896579 A JP14896579 A JP 14896579A JP S5671933 A JPS5671933 A JP S5671933A
Authority
JP
Japan
Prior art keywords
layer
film
type
heat treatment
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14896579A
Other languages
Japanese (ja)
Inventor
Shigeru Honjo
Shoichi Kitane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14896579A priority Critical patent/JPS5671933A/en
Publication of JPS5671933A publication Critical patent/JPS5671933A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1404—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material

Landscapes

  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To obtain a P type base layer having poor impurity variation by forming an insulating film having an opening on an N type semiconductor layer wherein a diffusion source including B stipulating the thickness is formed on the whole surface and B is diffused by heat treatment. CONSTITUTION:An oxide film 14 having a diffusion opening 15 is formed on the layer 12 side of a semiconductor layer 11 composing of an N<+> type layer 13 and an N<-> type layer 12 to make a film 16 by hardening the film 14 after applying a liquid diffusion source including B on the film 14 as thick as 2,800-3,500Angstrom . Next, heat treatment is applied at 900-1,200 deg.C under a mixed atmosphere of N2 and O2 having an O2 mixing rate of 10% or less and a P type later 17 is made by keeping the film 16 thickness of 1,500Angstrom or more. After the above procedure, an SiB layer 16' is left with the thickness of 40Angstrom or more on the layer 17 by using a diluted HF solution and the film 16 is removed. Then, the film 14 is renewed to a film 14' to apply heat treatment and the layer 17 is changed to a deep P type base layer 17' by diffusing B in the layer 16'. Next, a P<+> type base contact layer 18' is provided around the layer 17', an N<+> type base contact layer 18' in the layer 17' and an N<+> type emitter layer 19 in the layer 17' respectively and the surface of the film 14' is protected with an SiO2 film 20.
JP14896579A 1979-11-19 1979-11-19 Impurity diffusion to semiconductor substrate Pending JPS5671933A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14896579A JPS5671933A (en) 1979-11-19 1979-11-19 Impurity diffusion to semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14896579A JPS5671933A (en) 1979-11-19 1979-11-19 Impurity diffusion to semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS5671933A true JPS5671933A (en) 1981-06-15

Family

ID=15464616

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14896579A Pending JPS5671933A (en) 1979-11-19 1979-11-19 Impurity diffusion to semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS5671933A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62160718A (en) * 1986-01-08 1987-07-16 フィリップス　エレクトロニクス　ネムローゼ　フェンノートシャップ Manufacture of semiconductor device by diffusing dopant intosemiconductor substance from oxide of the dopant
EP0598438A1 (en) * 1992-11-17 1994-05-25 Koninklijke Philips Electronics N.V. Method for diffusing a dopant into a semiconductor
JPWO2013180244A1 (en) * 2012-05-31 2016-01-21 富士電機株式会社 Manufacturing method of semiconductor device
JP2020021766A (en) * 2018-07-30 2020-02-06 グローバルウェーハズ・ジャパン株式会社 Silicon wafer manufacturing method
US11290150B2 (en) 2017-05-03 2022-03-29 Assia Spe, Llc Systems and methods for implementing high-speed waveguide transmission over wires

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4944667A (en) * 1972-05-31 1974-04-26 Texas Instruments Inc
JPS49121476A (en) * 1973-03-20 1974-11-20
JPS5263666A (en) * 1975-11-20 1977-05-26 Toshiba Corp Boron diffusion to silicon wafers

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4944667A (en) * 1972-05-31 1974-04-26 Texas Instruments Inc
JPS49121476A (en) * 1973-03-20 1974-11-20
JPS5263666A (en) * 1975-11-20 1977-05-26 Toshiba Corp Boron diffusion to silicon wafers

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62160718A (en) * 1986-01-08 1987-07-16 フィリップス　エレクトロニクス　ネムローゼ　フェンノートシャップ Manufacture of semiconductor device by diffusing dopant intosemiconductor substance from oxide of the dopant
EP0598438A1 (en) * 1992-11-17 1994-05-25 Koninklijke Philips Electronics N.V. Method for diffusing a dopant into a semiconductor
JPWO2013180244A1 (en) * 2012-05-31 2016-01-21 富士電機株式会社 Manufacturing method of semiconductor device
US11290150B2 (en) 2017-05-03 2022-03-29 Assia Spe, Llc Systems and methods for implementing high-speed waveguide transmission over wires
JP2020021766A (en) * 2018-07-30 2020-02-06 グローバルウェーハズ・ジャパン株式会社 Silicon wafer manufacturing method

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