JPS5674753A - Concurrence processing circuit - Google Patents

Concurrence processing circuit

Info

Publication number
JPS5674753A
JPS5674753A JP15115179A JP15115179A JPS5674753A JP S5674753 A JPS5674753 A JP S5674753A JP 15115179 A JP15115179 A JP 15115179A JP 15115179 A JP15115179 A JP 15115179A JP S5674753 A JPS5674753 A JP S5674753A
Authority
JP
Japan
Prior art keywords
output line
circuit
nand logical
external output
nand
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15115179A
Other languages
Japanese (ja)
Other versions
JPS6217774B2 (en
Inventor
Takashi Minamitani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15115179A priority Critical patent/JPS5674753A/en
Publication of JPS5674753A publication Critical patent/JPS5674753A/en
Publication of JPS6217774B2 publication Critical patent/JPS6217774B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE: To selectively receive the input signal that has arrived earliest and also inspect the internal fault by itself, by providing an output of each NAND logical circuit to all the NAND logical elements except the group to which it belongs, and also using a two-wire system for the input/output signals.
CONSTITUTION: When the NAND logical circuit 11 has completed the variation of "1" to "0" earliest, "0" is provided to the inlets of the NAND logical circuits 13, 14, and therefore the value of the outputs 203, 204, remains "1". On the other hand, the NAND logical circuit 12 executes the variation of "1" to "0", and therefore, the value of the external output lines 301...304 becomes 1100 at last, and the request of CPU1 proves to have been acknowledged. Also, in case when the circuit 11 has broken down and its output line has been fixed to "1", the external output line 301 is fixed to "0", and when a request from CPU1 has been received, the input lines 101, 102 become "1", the NAND circuit 12 is inverted, and the external output line 302 becomes "1". That is to say, the value of the external output line remains 0100, and is not varied thereafter. In this way, it is possible to selectively receive the input signal that has arrived earliest and inspect the internal fault by itself.
COPYRIGHT: (C)1981,JPO&Japio
JP15115179A 1979-11-21 1979-11-21 Concurrence processing circuit Granted JPS5674753A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15115179A JPS5674753A (en) 1979-11-21 1979-11-21 Concurrence processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15115179A JPS5674753A (en) 1979-11-21 1979-11-21 Concurrence processing circuit

Publications (2)

Publication Number Publication Date
JPS5674753A true JPS5674753A (en) 1981-06-20
JPS6217774B2 JPS6217774B2 (en) 1987-04-20

Family

ID=15512468

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15115179A Granted JPS5674753A (en) 1979-11-21 1979-11-21 Concurrence processing circuit

Country Status (1)

Country Link
JP (1) JPS5674753A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5965355A (en) * 1982-09-10 1984-04-13 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Method and circuit for feeding interrupt request signal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5965355A (en) * 1982-09-10 1984-04-13 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Method and circuit for feeding interrupt request signal

Also Published As

Publication number Publication date
JPS6217774B2 (en) 1987-04-20

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