JPS5678148A - Resistance temperature compensation circuit - Google Patents
Resistance temperature compensation circuitInfo
- Publication number
- JPS5678148A JPS5678148A JP15436979A JP15436979A JPS5678148A JP S5678148 A JPS5678148 A JP S5678148A JP 15436979 A JP15436979 A JP 15436979A JP 15436979 A JP15436979 A JP 15436979A JP S5678148 A JPS5678148 A JP S5678148A
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- film
- wirings
- wiring
- insulation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/80—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors
- H10D86/85—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors characterised by only passive components
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
PURPOSE:To miniaturize a device, by a method wherein, when a No.1 and a No.2 resistance formed with a thick or thin film is formed on an insulation substance to form a resin temperature circuit, said resistances are formed in a two-layer structure such that they are thermally coupled together and electrically separated from each other. CONSTITUTION:Wirings 2-4 for resistance terminal, consisting of a conductor film, are formed on a ceramic substrate 1 at intervals to produce a given pattern, and a No.1 resistance R1 is adhered between the wirings 2 and 3 with the ends of the resistance laid at the surface ends of the wirings 2 and 3. The resistance R1 is covered with an insulation film 5, and a No.2 resistance R2, which ranges from the surface end of the wiring 2 to the end of the other wiring 4, is adhered onto the insulation film 5. If the resistance is a thin film, it is formed through the evaporation of an NiCr alloy, and in the case of the thick film, it is formed through the printing of paste, such a PdAg. This permits corresponding of a circuit to a sever wet property, and allows the reduction in an occupation area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15436979A JPS5678148A (en) | 1979-11-30 | 1979-11-30 | Resistance temperature compensation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15436979A JPS5678148A (en) | 1979-11-30 | 1979-11-30 | Resistance temperature compensation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5678148A true JPS5678148A (en) | 1981-06-26 |
Family
ID=15582647
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15436979A Pending JPS5678148A (en) | 1979-11-30 | 1979-11-30 | Resistance temperature compensation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5678148A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5817402A (en) * | 1994-07-29 | 1998-10-06 | Sekisui Kagaku Kogyo Kabushiki Kaisha | Covering sheet having minute unevenness on the surface thereof, methods of producing said sheet and a molding using said sheet |
| US5997675A (en) * | 1994-07-29 | 1999-12-07 | Sekisui Kagaku Kogyo Kabushiki Kaisha | Method of molding using a covering sheet having minute unevenness on the surface thereof |
| US6419778B2 (en) | 1996-05-23 | 2002-07-16 | Sekisui Kagaku Kogyo Kabushiki Kaisha | Covering sheet having minute unevenness on the surface thereof, methods of producing said sheet and a molding using said sheet |
| JP2002539634A (en) * | 1999-03-16 | 2002-11-19 | モトローラ・インコーポレイテッド | Printed wiring board having multilayer integrated thin film metal resistor and method of manufacturing the same |
-
1979
- 1979-11-30 JP JP15436979A patent/JPS5678148A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5817402A (en) * | 1994-07-29 | 1998-10-06 | Sekisui Kagaku Kogyo Kabushiki Kaisha | Covering sheet having minute unevenness on the surface thereof, methods of producing said sheet and a molding using said sheet |
| US5997675A (en) * | 1994-07-29 | 1999-12-07 | Sekisui Kagaku Kogyo Kabushiki Kaisha | Method of molding using a covering sheet having minute unevenness on the surface thereof |
| US6419778B2 (en) | 1996-05-23 | 2002-07-16 | Sekisui Kagaku Kogyo Kabushiki Kaisha | Covering sheet having minute unevenness on the surface thereof, methods of producing said sheet and a molding using said sheet |
| JP2002539634A (en) * | 1999-03-16 | 2002-11-19 | モトローラ・インコーポレイテッド | Printed wiring board having multilayer integrated thin film metal resistor and method of manufacturing the same |
| EP1082732A4 (en) * | 1999-03-16 | 2006-11-22 | Motorola Inc | Printed circuit board with a multilayer integral thin-film metal resistor and method therefor |
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