JPS5680869A - Address conversion associative buffer system - Google Patents

Address conversion associative buffer system

Info

Publication number
JPS5680869A
JPS5680869A JP15801679A JP15801679A JPS5680869A JP S5680869 A JPS5680869 A JP S5680869A JP 15801679 A JP15801679 A JP 15801679A JP 15801679 A JP15801679 A JP 15801679A JP S5680869 A JPS5680869 A JP S5680869A
Authority
JP
Japan
Prior art keywords
address
area
space
recognition number
address space
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15801679A
Other languages
Japanese (ja)
Inventor
Toshihisa Matsuo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15801679A priority Critical patent/JPS5680869A/en
Publication of JPS5680869A publication Critical patent/JPS5680869A/en
Pending legal-status Critical Current

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To enhance the action performance and simplify the data processing by dividing an address conversion associative buffer into a partially collected area allocated for one address space in a column direction.
CONSTITUTION: The address conversion associative buffer (TBL) 10 is divided into partially collected areas A, B... allocated for one address space in a column direction. The area A is corresponded to a real address mode and the area B is corresponded to a virtual address mode. When the output of the virtual address mode latch 11 is in high level, the recognition number such as three bits from the address space recognition number register 12 is gated and one area of the area B... is specified through an address register 14. Accordingly, in the case where the partial purging is required, it not required to examine all the entries of TBL10 by the recognition number of the space whether said entry is located in TBL10 and compare them but the inherent column groups corresponding to the address space is only cleared the action performance being enhanced and the data processing being simply done.
COPYRIGHT: (C)1981,JPO&Japio
JP15801679A 1979-12-07 1979-12-07 Address conversion associative buffer system Pending JPS5680869A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15801679A JPS5680869A (en) 1979-12-07 1979-12-07 Address conversion associative buffer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15801679A JPS5680869A (en) 1979-12-07 1979-12-07 Address conversion associative buffer system

Publications (1)

Publication Number Publication Date
JPS5680869A true JPS5680869A (en) 1981-07-02

Family

ID=15662421

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15801679A Pending JPS5680869A (en) 1979-12-07 1979-12-07 Address conversion associative buffer system

Country Status (1)

Country Link
JP (1) JPS5680869A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60116050A (en) * 1983-11-28 1985-06-22 Nec Corp Address conversion system
JPS6428757A (en) * 1987-07-24 1989-01-31 Hitachi Ltd Address converting buffer control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60116050A (en) * 1983-11-28 1985-06-22 Nec Corp Address conversion system
JPS6428757A (en) * 1987-07-24 1989-01-31 Hitachi Ltd Address converting buffer control system

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