JPS5687152A - Controller for common memory - Google Patents

Controller for common memory

Info

Publication number
JPS5687152A
JPS5687152A JP16400279A JP16400279A JPS5687152A JP S5687152 A JPS5687152 A JP S5687152A JP 16400279 A JP16400279 A JP 16400279A JP 16400279 A JP16400279 A JP 16400279A JP S5687152 A JPS5687152 A JP S5687152A
Authority
JP
Japan
Prior art keywords
common memory
address
data
parity
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16400279A
Other languages
Japanese (ja)
Other versions
JPS6042977B2 (en
Inventor
Yoshiharu Taki
Masato Suyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
NTT Inc
Original Assignee
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Nippon Telegraph and Telephone Corp filed Critical Hitachi Ltd
Priority to JP54164002A priority Critical patent/JPS6042977B2/en
Publication of JPS5687152A publication Critical patent/JPS5687152A/en
Publication of JPS6042977B2 publication Critical patent/JPS6042977B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE: To inhibit the memory access, by detecting the parity check of address and data with the common memory controller, storing the processor name producing the parity error, and detecting the parity error.
CONSTITUTION: One of requests 1 from each processor to the common memory is selected at the access request selection circuit 2, and it is set to the corresponding memory permission FF3. Further, in case of write-in to the common memory, based on the content set to FF3, the address and data of processor is selected with the address selection circuit 5 and the write-in data selection circuit 10. Next, the parity of address and dta is checked at the address and write-in data parity check circuits 6, 9, error display FF22 is set via the gate 21 when the error is detected, the access inhibition signal 24 is transmitted to the common memory via the gate 23, and the access to the common memory is inhibited.
COPYRIGHT: (C)1981,JPO&Japio
JP54164002A 1979-12-19 1979-12-19 common memory controller Expired JPS6042977B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54164002A JPS6042977B2 (en) 1979-12-19 1979-12-19 common memory controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54164002A JPS6042977B2 (en) 1979-12-19 1979-12-19 common memory controller

Publications (2)

Publication Number Publication Date
JPS5687152A true JPS5687152A (en) 1981-07-15
JPS6042977B2 JPS6042977B2 (en) 1985-09-26

Family

ID=15784884

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54164002A Expired JPS6042977B2 (en) 1979-12-19 1979-12-19 common memory controller

Country Status (1)

Country Link
JP (1) JPS6042977B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5955557A (en) * 1982-09-24 1984-03-30 Nec Corp Shared memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5955557A (en) * 1982-09-24 1984-03-30 Nec Corp Shared memory device

Also Published As

Publication number Publication date
JPS6042977B2 (en) 1985-09-26

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