JPS568848A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPS568848A JPS568848A JP8425779A JP8425779A JPS568848A JP S568848 A JPS568848 A JP S568848A JP 8425779 A JP8425779 A JP 8425779A JP 8425779 A JP8425779 A JP 8425779A JP S568848 A JPS568848 A JP S568848A
- Authority
- JP
- Japan
- Prior art keywords
- region
- wiring
- films
- polycrystalline
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To facilitate the formation of a low resistance polycrystalline Si wiring and a wiring within an element by simultaneous impurity diffusion into a polycrystalline Si region and a wiring region within an element without any influence on source and drain regions. CONSTITUTION:An Si nitride film 34 is formed on a P-type Si stubstrate 31, and by utilizing it as a mask a channel stopper 32 and a field oxide film 33 are formed. Next after the film 34 of a region where an element region is to be formed is removed, an Si oxide film 35 which is to be a gate insulation is formed, and on it patterned polycrystalline Si layers 36G, 36C and Si nitride films 37G, 37C are formed. Next by utilizing films 34, 37G, 36G as a mask an N-type impurity diffusion region 38 which has shallow junction depth and is to be source and drain is formed. Next films 34, 37G, 37C are removed and in the same time when an N- type diffusion layer 40 which has deep junction depth and is to be a wiring within an element is formed, films 36G and 36C are also changed to have a low resistance through diffusion of an N-type impurity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8425779A JPS568848A (en) | 1979-07-03 | 1979-07-03 | Manufacture of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8425779A JPS568848A (en) | 1979-07-03 | 1979-07-03 | Manufacture of semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS568848A true JPS568848A (en) | 1981-01-29 |
| JPS6154253B2 JPS6154253B2 (en) | 1986-11-21 |
Family
ID=13825394
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8425779A Granted JPS568848A (en) | 1979-07-03 | 1979-07-03 | Manufacture of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS568848A (en) |
-
1979
- 1979-07-03 JP JP8425779A patent/JPS568848A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6154253B2 (en) | 1986-11-21 |
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